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Design of bias circuit for LNA.

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1990

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I am designing LNA at 2.4GHz using ATF541432a. I have designed matching circuitary on input and output side.
Now i am left with Bias Circuit design.
How can i calculate values of L(for RF block) and C(to block DC)?
And if i do voltage divider circuitary then will it affect noise performance of LNA?
.....
Thanks & Regards
 

BigBoss

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RFC value should be 10 times as a rule of thumb of the load by caring about SRF of the RFC.
C Coupling capacitor should be choosen regarding to SRF and use high quality SMD components.Matching can also be considered with this capacitor, that's why its value depends on the esigner.
If this voltage divider ( or attenuator ) will be placed before LNA, its attenuation will be directly added to NF as a first term.If it's not, it will affect a bit but not much.
 

1990

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I have designed LNA at 2.4GHz with Input and Output matching networks.
I am not getting proper gain, vswr and NF ALSO due to some silly mistakes.
Point out the mistakes...

Thanks and Regards
scematic.pngResult.png
 

vfone

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I don't know if you use the right non-linear model for ATF54143, but check the datasheet for the Vgs nominal voltage, which I think should be about 0.5V.
Initially don't use any input/output LC matching networks, and just a series cap at the input and a series cap at the output, and bias the gate through a 100k resistor from a separate DC supply voltage.
 

1990

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Actually i have used s2p file for 2V and 5mA.
As u suggest, without matching network i got the results with 2.9dB gain.
And the gain provided at 50ohm termination is above 12dB.
...
I want to know
What is problem when matching network is attached?

& Thank u.
 

BigBoss

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Actually i have used s2p file for 2V and 5mA.
As u suggest, without matching network i got the results with 2.9dB gain.
And the gain provided at 50ohm termination is above 12dB.
...
I want to know
What is problem when matching network is attached?

& Thank u.

If you used s-parameters, you don't have to use bias circuit.Connect just s-parameter block and matching circuits,ports..
I don't know your matching circuit is correct or not but there shouldn't be a series resistance at the gate.It will drop the gain..
I hope you know well how to design a matching circuit...
 

1990

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thank you bigboss ,
i have got results by designing matching network using distributive element and without any bias circuit.....
.....
can u tell me, how a matching network is designed to terminate the harmonics specially 3rd for LNA?

Thanks and Regardd
 

BigBoss

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thank you bigboss ,
i have got results by designing matching network using distributive element and without any bias circuit.....
.....
can u tell me, how a matching network is designed to terminate the harmonics specially 3rd for LNA?

Thanks and Regardd

You have very limited play ground at input side of the LNA due to Noise Matching but you can create a notch at 3rd harmonic at the output if the bandwidth is not too very wide.There are some different techniques like "creating zero" in the matching circuit that will bring nulling effect at 3rd harmonic but it doesn't work every time.
 

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