Design of an OTA in Subthreshold

[s_babayan]

Dear all

I'm going to simulate an ultra-low power OTA in Subthreshold region in 0.18u CMOS technology but the simulation results are not very good I've heard that Bsim3 model in Hspice doesn't support subthreshold region? anybody knows exactly which model is approperiate? or if you have its library would you plz share it with me as well"

Regards,

Samaneh

 

[elbadry]

You can check the spice-model files provide by the foundry to check for how well the subthreshold region is modeled. I think in 0.18 and beyond sub-threshold is well-modeled as it is needed for leakage estimation.

 

[leohart]

You can check the spice-model files provide by the foundry to check for how well the subthreshold region is modeled. I think in 0.18 and beyond sub-threshold is well-modeled as it is needed for leakage estimation.

Hi,how to confirm that with only a model file ? I'm using a 0.6um process

 

[thcm]

Bsim3 is only not very accuracy at the transition area from sub-threshold to strong inverstin area. However for most cases, the issue possibly stems from your design. my suggest:1) as Elbadry said, using foundry data to confirm how well the device is modeled, if necessay using EKV model. 2) check your circuitry, bias it in real subthreshold region instead of in the transistion area.

 

[analog123]

Maybe you should check your design not to suspect the Bsim3 model.

 

[umagne]

Since February 2011 it'll be available on JSSC the design methodology of Subthreshold Voltage References, its DOI is 10.1109/JSSC.2010.2092997