Design of a comparator without undetermined output

[hans_r]

Hi,

i'm designing a comparator for a 12-bit AD-converter. I'm having some problems concerning the driving of the digital blocks after the comparator, and have these thoughts about it:

The comparator should always output a 0/1, otherwise the digital block will go in an undetermined state.
Considering the comparator as an amplifier:
Since the difference voltage at the input of the comparator can be randomly small, there will always be cases when the output of the comparator is not high/low enough to be considered as a logic 1/0, and therefore I can not drive the next stage!
Adding an inverter does not help, since the inverter will also go in undetermined state.
The idea is that the comparator should latch to a digital value, right? Is a schmitt trigger the solution?

Does anyone have any idea how to solve this? I guess it is a basic analog-digital interfacing problem!
Kind regards!

Hans

 

[FvM]

otherwise the digital block will go in an undetermined state

Not necessarily. The behavour should be analyzed in detail.

A comparator is basically a decision function. Near the threshold, the result becomes accidentally. If the ADC logic is able to make a decision anyway, e.g by the latching the comparator state in a SAR controller there won't be a problem. For fast ADCs, metastability possibly has to be considered. You would want to assure, that the uncertainty doesn't spread over multiple LSB.

 

[hans_r]

I'm making a ramp ADC: the comparator should compare the input voltage with a ramp. The output of the comparator is used as memory_enable signal to store the ramp-value in a memory.
For now, I'm just using an open-loop amplifier as a comparator. If the voltage-difference is to small, the output of the comparator will be Vdd/2+small signal, and will do something weird to the memory?! I want the comparator to output a 0 or a 1 if the voltage difference is to small ( 0 or 1 does not matter, since the quantization error will only be ±Vlsb/2).
What circuit can realize this need?

 

[FvM]

Storing a ramp counter value involves synchronous digital logic. The comparator value needs to be registered to the clock, otherwise you get unpredictable values in any case.

 

[hans_r]

Even if I register it to the clock, this does not solve my problem?

 

[crutschow]

I'm making a ramp ADC: the comparator should compare the input voltage with a ramp. The output of the comparator is used as memory_enable signal to store the ramp-value in a memory.
For now, I'm just using an open-loop amplifier as a comparator. If the voltage-difference is to small, the output of the comparator will be Vdd/2+small signal, and will do something weird to the memory?! I want the comparator to output a 0 or a 1 if the voltage difference is to small ( 0 or 1 does not matter, since the quantization error will only be ±Vlsb/2).
What circuit can realize this need?

If one of the comparator inputs is a ramp, then it won't have a metastable state. A metastable comparator state could only occur if the two voltages are static. The comparator will start to change state when the ramp voltage reaches the input voltage and will complete the state change when the difference between the two voltages is equal to the comparator output voltage change divided by the comparator gain. The time for the comparator to change will be determined by the ramp voltage slope (dV/dt) and the comparator gain.

It may oscillate as it's going through the comparison point due to intrinsic circuit noise if the comparator gain is high enough but that's a different possible problem. A small amount of hysteresis can eliminate that.

 

[FvM]

Even if I register it to the clock, this does not solve my problem?

Which problem isn't solved? All existing ramp converters, e.g. dual slope are working this way.