Design flow in vhdl/verilog (in Cadence)

[preet]

required design flow?

hi all,

is it possible to make design in vhdl/verilog which can be converted into layout and canbe integrated with previous manual analog layout design?

which tools r needed in cadence methodology?

what should be the tool design flow?

regards
Preet

 

[aravind]

required design flow?

u can write verilog-A code and simulate using spectra in icfb tool
and see it in layout form.

otherwise verilog/vhdl do Physical design using soc encounter and take def file into icfb and see layout editor

 

[draz]

Re: required design flow?

i doubt if you can take Def into icfb

take the vhdl/verilog to phisical deisgn and dump a gdsii .

you can use icfb or calibre drv to view the gds

 

[preet]

Re: required design flow?

I dont Want to view but i want to use with other design.

Regards
Preet

 

[urslen]

Re: required design flow?

is it possible to make design in vhdl/verilog which can be converted into layout and canbe integrated with previous manual analog layout design?

which tools r needed in cadence methodology?

what should be the tool design flow?

Yes, generally many designs will be going through this way. The analog designer will be preparing his (manual) design and the digital design will consider those as analog IP blocks while floorplannin and P&R. While stream in (in virtuoso, icfb tool) both digital and analog design with full physical details will be placed together. here i have just tried to give a outline.

Analog IP Development
(it may include initially abstract view for the analog IPs, which will be useful for PD engineer to place the IP as a black box and close the floorplanning trials; then ofcourse the final release of the analog IP blocks will be given to PD team with all the physical details)

Digital Design
Simulteniously the digital designer will be coding, simulating and synthesize the digital design part. He will prepare the initial netlist which will be gien to PD (Physical design) team for their floorplan trials. After fixing all the synthesizing issues, and STA, they delever the final netlist to the PD team.

Physical Design
after the initial analysis of the library and gathering all the details like pad placement guidelines, estimated die size; the PD team will be working with the initial floorplanning with the initial analog IP and the initial netlist from the digital designer to freeze the floorplan (also powerplan, IR drop and EM analysis using VoltageStorm).

then after getting the final netlist from the digital designer, PD team will do all the routine iterative works (Placement, CTS, Global routing, timing closure, initial DRC, detailed routing, again timing closure, ..... stream in and many more). Till now you can work with the cadence Encounter tool.

you can find this flow from many posts in this forum.

Mainly to give your answer, while importing def to the physical details (eg. in icfb from Cadence virtuoso package) you have to provide the analog physical details which was considered as the black box till now along with the technology gds files. Here only your digital design will be placed along with the analog part physically. Remember, while doing floorplan, you have to follow the analog blocks placement guide (if there any constarint in placing them). after bringing down your full design to the complete physical information, DRC, LVS should be checked.

Finally the timing closure should be met again, and here some more signoff tools comes in picture. When your design proves through signoff tools, your final GDSII is out (stream out). cake cutting time....

Remember I have given only outline and gave the tool list mainly from cadence suit. Other tool vendors also provide very good tools (like PT, DC, Blast series, Astro, calibre, verplex for formal verification etc.). For more information on that... wait for some more tool experts to light in here....

for more details on the encounter flow you can check the following topic discussion