Design considerations of using NFET or PFET for synchronous buck converters

[bhl777]

Hi All, when we design synchrounous buck converters, some people use two NFETs in the power train, while some other people use PFET as the upper FET and NFET as the lower FET.

Using these different FET selections will have different gate drive circuits. I am wondering what is the key consideration that determines the choice of two NFETs or NFET+PFET?

Thank you!

 

[dick_freebird]

NFET high side requires a bootstrap capacitor and a
flying high side predrive chain, but offers much better
switch on-resistance per area.

PFET is simple and can make peak current mode
control current sensing simple (think SenseFET). The
high side drive is now within, rather than outside the
rails. But expect ~2-3X the area (though less of a
concern if the application is narrow duty cycle and
high side conduction losses less important).

Since NFET will be smaller, switching losses ought
to be better.

Last rodeo, we had examples of each in silicon in
hand and went with the PMOS high side because
of the current mode control implementation aspects.

 

[asdf44]

Voltage is also a big consideration.

PFET gate drive is only simple if ON=GND which means the source voltage needs to be above the turn on threshold (~5V and below the Vgs breakdown 8-20V). Once anything fancy is required the circuit might as well have a bootstrap cap and use a NFET for its other advantages.

 

[treez]

if your voltage is low then go for a linear.com sync buck with drivers on the chip......then you can easily use nfets....nfets are usually better than pfets in terms of rdson etc.

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If its high voltage and /or high power than go for nfets and pulse transfmr /charge pump drive etc