I still don't know how you can claim there wasn't a problem. What simulation tool are you using, because Xilinx ISE/Vivado and Modelsim all complained with the mixed case IndexX and the indexX declarations not being the same. What ever simulation tool you are using must have problems with adhering to the Verilog LRM.
Given the poor track record of your simulator, I suspect it can't handle the mixed simulation of Verilog TB and VHDL netlist. Write out your netlist in Verilog and see if that fixes your problem.
If there is a problem with the VHDL instance in the Verilog then you should have been able to see that by examining the inputs/outputs in both parts of the hierarchy. You've never indicated if you've traced the source of the X's back to anything in the simulation, I've been assuming (probably wrongly) that you've tried this but couldn't determine why it went X. You could also try a small testcase design like a 4-bit case and see if you can't trace the X's back through that netlist. I understand a 256 case statement is a very large logic cone so it would be hard to trace back through the simulation of the netlist.
Unfortunately I probably make way too many assumptions on peoples debugging skills (I usually assume they are decent, and decent to me is probably excellent to most), so excuse me for not having made these suggestions (like a simpler testcase) originally.
