Design Compiler Input to Output Delay Constraints for A Shift Register

[ranaya]

Hi All,

I have a following type of shift register composed of MUXs and Flip-Flops.



So basically the input MUX of every Flip-Flop chain feeds the data to the chain and the data can also be interchanged between two parallel chains using the same MUXs. I synthesized the design in Design Compiler using following constraints:

set OB_NAME "SHFT_REG"
set CLK "clk"
set clk_pr 10

elaborate ${OB_NAME}

if { ! [link] } {
  puts "Error: Failed to link 'Design'."
  exit 1
}

check_design
uniquify

create_clock ${CLK} -period ${clk_pr}
set_input_delay -max 0.3 -clock ${CLK} [remove_from_collection [all_inputs] [get_ports ${CLK}]]
set_output_delay -max 0.3 -clock ${CLK} [all_outputs] 

set_load 0.010 [all_outputs] 
set_clock_uncertainty 0.050 ${CLK}
set_propagated_clock ${CLK}	
set_max_delay 100 -from din[0] -to yout[15]

However the report_timing can only generate the timing reports for clock to Q delays of all FFs. i.e. all inputs to all outputs report_timing reports "no paths" !
How can I generate timing reports for these paths ? Or how can I set the constraints for the input to outputs of this type of design ?

Thanks
Anuradha

 

[KlausST]

Hi,

I´m no expert in this area.

But I assume there is no need for generating these timings.

All DFFs should be driven from the same clock. Then there is just the "single" delay from clock edge to ouput.
For sure you need to fullfill data setup timing requirement.

Data_in to Data_out timing is determined by the clock (edge) ... and the n stages (DFFs) between input and output.

****

Klaus

 

[ranaya]

Dear Klaus,

Hi, thanks for your reply. Yes this is just a "pipelined" like design without any comb. clouds in between. But suppose that the final input to output delay also matters (i.e. for physical design experiments). So that the downstream tools will decide which FFs (and clock tree components) to be used (depending on the setup as you stated and hold depending on the uncertainty) from the cell library to meet the final requirement. I think set_max_delay 100 -from din[0] -to yout[15] command is there for this type of requirement, isn't it ? So I expected the DC to report full input-to-output path delays. However it does not seem doing that.

Anuradha

 

[kungchuking]

I think you already constrained your input/output ports by:

set_input_delay -max 0.3 -clock ${CLK} [remove_from_collection [all_inputs] [get_ports ${CLK}]]
set_output_delay -max 0.3 -clock ${CLK} [all_outputs]

May be you can try:

group_path -name In_to_Out -from [all_inputs] -to [all_outputs]
report_timing -group In_to_Out -max_paths 50 -transition_time -nets

to report all combinational paths from input to output.

PS: Not sure if that's what you want.

 

[ranaya]

group_path -name In_tut -from [all_inputs] -to [all_outputs]
report_timing -group In_tut -max_paths 50 -transition_time -nets
[/CODE]
to report all combinational paths from input to output.

PS: Not sure if that's what you want.

This is indeed what I want to do. And I have tried it already, without specifying a path group for that. But even with the path group and number of max paths set to a number, let's say 50, all I get is following :

****************************************
Report : timing
        -path full
        -delay max
        -group In_to_Out
        -max_paths 50
Design : SHFT_REG
Version: O-2018.06
Date   : Thu May  7 13:47:37 2020
****************************************

Operating Conditions: PVT_0P6V_25C   Library: BLAA_0P6V_TT_25C
Wire Load Model Mode: top
No paths.

1

 

[kungchuking]

Could you provide your RTL design and synthesis log?

 

[ThisIsNotSam]

This is normal. STA reports in->flop, flop->flop, flop->output. you don't have in->out paths.

what am I missing?

 

[kungchuking]

My bad, I didn't realize that group_path doesn't work on In_tut path.

Correction: the following will work

report_timing -from [all_inputs] -to [all_outputs]