Design Compiler error while compiling vhdl design..

[priyanka24]

Hi...

i have implemented my VHDL code and simulated it in VCS correctly.

but in Design Compiler alalysed, elaborated and specified clock properly. when in DC when did compile design then design vision is closed and me got following error:::



can anybody tell where am going wrong and what is wrong???

 

[FvM]

Strictly spoken, there's apparently a Synopsys DC bug.

In most, cases this kind of internal errors is brought up by unexpected operations in the code, e.g. unconstrained for loops and other non synthesizable contructs. You may want to post the code to allow checking it with other design compilers.

 

[hbeck]

I got the same error case some weeks before and from my point of view this seems to be an operating system problem. Are there any updates installed that need a system restart and you forgot that?

My DC 2011.09 runs perfect on one Machine (CentOS 6.2) and crashed with the same error on another machine (same os, same dc, same rtl, same scripts, but with a lot of os updates that requires a restart). After restart everything works fine on both machines!

 

[poluekt]

- check design constaraints
- check DesignWare including (dw_foundation.sldb must be included in link_library)
- try commands compile -incremental (compile_ultra -incremental)