Design Compiler and RTL compiler give opposite results

[Hang Zhang]

I'm comparing two designs, and both designs are synthesized using both Cadence's RTL compiler and Synopsys' Design compiler

Same input netlists, same constraints, and same technology library.

Design A is faster then design B using RTL Compiler, but slower than B using Design compiler.

Any ideas why this would happen?

 

[beeflobill]

Are you asking why the tools took different amounts of time to do the synthesis, or are you asking why the synthesis result was a faster digital design?

Either way, I would think this is a hard question to answer without having some pretty deep knowledge about how each of the synthesis tools are implemented and some more specific info about your input RTL. Were the outputs from the different tools significantly different?

Some ideas? One tool was simply lucky, in that how it was implemented it stumbled onto a solution that satisfied the input constraints faster that the other one, or was just lucky to create a faster solution. Perhaps one tool had a specific capability to recognize and synthesize a particular digital structure that the other tool did not. Maybe one tool was simply coded more efficiently than the other, or has heuristics to help it skip unneeded steps when it can.

 

[maulin sheth]

Can you inform the faster terms in what?