I am working on master thesis in SDR based on FPGA.
I have been trying to work out how to design the CIC / FIR filter pair in
the DDC section of this design.
I need a help to understand the main operation of these filters.
Hopefully someone out there will be able to help.
you can download some paper from IEEE which can help you much.
An economical class of digital filters for decimation and interpolation.pdf
This paper is a good paper and it introduces CIC filter first.