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Design challenge under lower supply voltage

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eexuke

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Dear all,
For a 0.18um design with 1.8v standard supply voltage, and with far more than enough time margin, I want to lower down my supply voltage to reduce power. For example, if I reduce the supply voltage to 0.9~1V, what I should pay attention during my physical design? Currently I think IR drop may be the critical issue,do you have any other considerations?
Many thanks!
 

linuxluo

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hi,
I am doing digital design.
so first you have to make sure your lib support such voltage.
and as to 0.18um, becoz your voltage margine is shorten from 1.8 to 1.0v, so SI effect should be seriousely treated.
 

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