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Design challanges in 90nm

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Sadegh.j

Sadegh.j

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Hey

Does anyone know about some design challenges in 90nm, or can give me a reference to read about it?
 

Visit Cadence and Mentorgraphics site ... there you can get some very good reference and papers.
 

usually from 90nm & below, you should take into account the leakage problem , as now , gate may hold significant current , more advanced technologies like 45nm may take that into account by using high K material
 

HI RFDE

Do you have any references?

Thanks
 

Sadegh.j said:
Hey

Does anyone know about some design challenges in 90nm, or can give me a reference to read about it?
Click to expand...

The leakage current should be the most critical challenge.
Because the current consumation will be increase obviously.
 

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