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design and implementation of 16 bit processor

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karnakar_k

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hi,
iam designing 16 bit processor in verilog. I have interfaced processor with memory. initially iam storing instructions in memory. when reset is pressed my output is made 0; after that the instructions stored in memory are executed sequentially. In simulation every thing is working fine. But when dumped in hardware (virtex 5) it is not working. The bit file has around 77 warnings for all signals as


WARNING:physDesignRules:372 - Gated clock. Clock net
rw/memory is sourced by a combinatorial pin. This
is not good design practice. Use the CE pin to control the loading of data
into the flip-flop. (this is for only rw signal)



I have tried using chip enable for memory but the warnings are same. But when the clock is used the code is not working properly.

Here is code for memory



module ram(cs,data,addr,rw,sel,ready);

input [15:0]addr;
inout [15:0]data;
wire [15:0]data;
input sel,rw,cs;

output ready;

reg ready;
reg [15:0]dataout;
reg [15:0]array[63:0];





initial
begin
array[0]=16'h1003; //loadi r3 <- 0010
array[1]=16'h0002;
array[2]=16'h1001; //loadi r1 <- 0004
array[3]=16'h0004;
array[4]=16'h1002; //loadi r2 <- 0003
array[5]=16'h0003;

array[6]=16'h1c03; //inc r3
array[7]=16'h2003; // dec r3
array[8]=16'ha01a; //multiply r2 and r3
array[9]=16'h2c35; // xor r5 and r6
array[10]=16'h2411; //and1
array[11]=16'h2811; //or
ready=1;
end

always @ (cs,sel,rw,addr)
begin
if(cs==1)
begin
ready=0;
if(rw==0)
begin
dataout<=array[addr];
end
else
array[addr]<=data;
ready=1;
end
end



assign data=sel&(~rw)?dataout:16'bZ;


endmodule
 
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