Design about high speed comparator in sigma delta ADC

[megzhuy]

Is there anybody who can tell me how to determine the minimum gain in two order sigma delta ADC.

 

[bear7679]

I think the compartator gain depend on your ADC's accuracy and application. If your ADC is used as DC measurement, I think the comparator's gain must be large.
If your two-order ADC's gain is Ads(quantization noise), then the comparator's offset must be less than 1LSB*Ads.

 

[Btrend]

Is there anybody who can tell me how to determine the minimum gain in two order sigma delta ADC.

I also want to know the answer of this topic.
Below is my thought :
In nyquist rate comparator
said, if SNR required is 80dB, the minimal quantization noise is 1/10000 V= 0.1mV (if the signal is 1V). then ur comparator should be able to distinguish voltage difference level down to 0.1mV, i.e. gain >= 80dB.
In sigma delta comparator:
if SNR is 80dB, the quantization noise can be reduced by oversampling method and sigma-delta modulator.
SNRmax=6.02*N+1.76-12.9+50*log(OSR) ... for 2-order sigma-delta modulator. (from Martin's book)
where OSR is the oversampling ratio : fs/2f0, N is the bits (resolution) required for ur comparator.
So, let 80=6.02*N+1.76-12.9+50*log(OSR)
if OSR=64, N=0.13 ==> choose N=1
if OSR=32, N=2.6 ==> choose N=3
if OSR=16, N=5.13 ==> choose N=6

From the above, u only need a rough comparator (1 bit resolution) in OSR=64 situation. the equivalent gain of the comparator is 2.
if OSR=32, the gain of comparator is 2^3=8;
if OSR=16, the gain of comparator is 2^6=64;

hope this result will be helpful.