cris2
Member level 1
Hello,
I have to do a scool project with the folowing topic:
"The idea of this project is to design a simple pipelined processor, Mini-MIPS, which is a subset of the 32-bit MIPS architecture as described in the textbook (Appendix A). Mini-MIPS uses the same 3 instruction formats of MIPS (R, I and J-types) to implement following 10 instructions: ADD, SUB, ADDI, SUBI, AND, OR, LW, SW, JR, and BEQZ. It will be assumed that the memory can be accessed in one clock cycle and works synchronously with the CPU (i.e., no need to provide explicit external memory control).
You should proceed step by step towards building the CPU by:
Understanding and analyzing the behavior of each instruction
Defining the detailed micro-operations and encoding of each instruction
Identifying which operations will be parallelized to obtain the pipelined CPU
Designing a detailed block diagram of the CPU
Partitioning the blocks into Datapath and Control Unit
Designing each of the blocks of the Datapath at the RT- level (no need to go at the gate level)
Designing the Control Unit including: decoding, datapath control, pipeline control, etc. (you may leave the control design at the FSM level)
Putting all blocks together to get the full CPU
Simulate your CPU with one test assembly program
You should write a detailed project report documenting above tasks and give a presentation at the end of the term illustrating the main challenges you faced in this project.
Special attention should be given to the pipelined design. Your design should be structural hazards free. Data hazards should be solved with the bypassing technique + a one-slot delayed load. Control hazards are assumed to be solved using a one-slot delayed branch.
Starting from a paper-and-pencil design of the major blocks, it is suggested you implement your CPU using VHDL or Verilog (e.g. within CADENCE or SYNOPSYS). "
Could somebody help on that? Any info will be appreciated!
Thank you,
Cris2
I have to do a scool project with the folowing topic:
"The idea of this project is to design a simple pipelined processor, Mini-MIPS, which is a subset of the 32-bit MIPS architecture as described in the textbook (Appendix A). Mini-MIPS uses the same 3 instruction formats of MIPS (R, I and J-types) to implement following 10 instructions: ADD, SUB, ADDI, SUBI, AND, OR, LW, SW, JR, and BEQZ. It will be assumed that the memory can be accessed in one clock cycle and works synchronously with the CPU (i.e., no need to provide explicit external memory control).
You should proceed step by step towards building the CPU by:
Understanding and analyzing the behavior of each instruction
Defining the detailed micro-operations and encoding of each instruction
Identifying which operations will be parallelized to obtain the pipelined CPU
Designing a detailed block diagram of the CPU
Partitioning the blocks into Datapath and Control Unit
Designing each of the blocks of the Datapath at the RT- level (no need to go at the gate level)
Designing the Control Unit including: decoding, datapath control, pipeline control, etc. (you may leave the control design at the FSM level)
Putting all blocks together to get the full CPU
Simulate your CPU with one test assembly program
You should write a detailed project report documenting above tasks and give a presentation at the end of the term illustrating the main challenges you faced in this project.
Special attention should be given to the pipelined design. Your design should be structural hazards free. Data hazards should be solved with the bypassing technique + a one-slot delayed load. Control hazards are assumed to be solved using a one-slot delayed branch.
Starting from a paper-and-pencil design of the major blocks, it is suggested you implement your CPU using VHDL or Verilog (e.g. within CADENCE or SYNOPSYS). "
Could somebody help on that? Any info will be appreciated!
Thank you,
Cris2
