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Design a simple pipelined processor

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cris2

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Hello,

I have to do a scool project with the folowing topic:

"The idea of this project is to design a simple pipelined processor, Mini-MIPS, which is a subset of the 32-bit MIPS architecture as described in the textbook (Appendix A). Mini-MIPS uses the same 3 instruction formats of MIPS (R, I and J-types) to implement following 10 instructions: ADD, SUB, ADDI, SUBI, AND, OR, LW, SW, JR, and BEQZ. It will be assumed that the memory can be accessed in one clock cycle and works synchronously with the CPU (i.e., no need to provide explicit external memory control).
You should proceed step by step towards building the CPU by:

Understanding and analyzing the behavior of each instruction
Defining the detailed micro-operations and encoding of each instruction
Identifying which operations will be parallelized to obtain the pipelined CPU
Designing a detailed block diagram of the CPU
Partitioning the blocks into Datapath and Control Unit
Designing each of the blocks of the Datapath at the RT- level (no need to go at the gate level)
Designing the Control Unit including: decoding, datapath control, pipeline control, etc. (you may leave the control design at the FSM level)
Putting all blocks together to get the full CPU
Simulate your CPU with one test assembly program
You should write a detailed project report documenting above tasks and give a presentation at the end of the term illustrating the main challenges you faced in this project.
Special attention should be given to the pipelined design. Your design should be structural hazards free. Data hazards should be solved with the bypassing technique + a one-slot delayed load. Control hazards are assumed to be solved using a one-slot delayed branch.

Starting from a paper-and-pencil design of the major blocks, it is suggested you implement your CPU using VHDL or Verilog (e.g. within CADENCE or SYNOPSYS). "

Could somebody help on that? Any info will be appreciated!

Thank you,

Cris2
 

cris2

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Is this the wrong place to ask this question?
 

cmos babe

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yousuf

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Hi,

Can you be more specific as to which tools are you going to use, Verilog/VHDL is too generic, also what is the level of your competency, i.e. what other projects have you successfully implemented in hardware. Just to get an idea of your skills.


Later.
 

cris2

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Thanks cmos babe, at the moment you sent the message I was reading it and the other one written by the same authors:

https://www.amazon.com/exec/obidos/...bs_b_2_1/103-4219348-5063812?v=glance&s=books

The second one is the course textbook and the first one is recommended as supplementary reading.

Yousouf, the tools are specified: Synopsys or Cadence, but are not so important. We can use any other tool (i.e. Altera Quartus II, Modelsim, Active HDL from Aldec,…).

I prefer to do the coding in VHDL and my level of competency has nothing to do with the topic…So if you can help do it and let me decide if the info is to easy or to complicated for my understanding abilities!

I would need some project examples with code, especially the control unit.

Cris2
 

cmos babe

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cris2 said:
Thanks cmos babe, at the moment you sent the message I was reading it and the other one written by the same authors:

h**p://www.amazon.com/exec/obidos/tg/detail/-/1558605967/qid=1129219779/sr=2-1/ref=pd_bbs_b_2_1/103-4219348-5063812?v=glance&s=books

The second one is the course textbook and the first one is recommended as supplementary reading.

Yousouf, the tools are specified: Synopsys or Cadence, but are not so important. We can use any other tool (i.e. @ltera qu@rtus II, Modelsim, Active HDL from Aldec,…).

I prefer to do the coding in VHDL and my level of competency has nothing to do with the topic…So if you can help do it and let me decide if the info is to easy or to complicated for my understanding abilities!

I would need some project examples with code, especially the control unit.

Cris2

I suggest that you warm up for control unit design by understanding FSMs well and understanding how to write VHDL code that descripes them..The CU is an FSM that outputs the control signals depending on the state... for example in the fetch state, it will set the "read memory" control signal and the "write enable" control signal of the "instruction register" so that the instruction is stored there ,it will also set the necessary control lines needed for incrementing the Program Counter...
 

cris2

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The hazards are annoying me…
 

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