Design a flash adc with these specifications

[Osawa_Odessa]

Hi,
I want to design an ADC with these specifications:
- Flash ADC
- f_in= 400MHZ
- ENOB > 7.5
Is this hard because I have no experience in this? I am learning and hope can do it after three months.
Could you tell me your opinions and suggest some good materials?
Thanks.

 

[dick_freebird]

First, you need a comparator with a low-overdrive prop
delay of maybe 1nS - if you want to allocate 1nS to input
settling time including kickback noise, and 0.5nS to the
encode logic. If you want single cycle latency which is
the whole idea of a flash.

"Low overdrive" means VIN/2^(N+1) roughly - give it half
of the "bin" voltage for overdrive and allocate the rest to
various individual comparator input errors.

I have never made a comparator that good, myself - if
I called it 2.5V in then that's a 10mV bin and a 5mV
overdrive. Says autozero and/or clocked regenerative
comparator, to me. I'd focus on whether you can make
one comparator capable of playing its part in the bigger
picture.

But you might also get some indication by looking at
ADCs commercially available, and if you can't find a
one, in similar technology to what you're intending to
use, then figure you're unlikely to achieve what all of
industry could not. Surely, not inside the semester.