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Design a First-In-First-Out (FIFO) buffer that can store up to 8 data words received

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macgradywk

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QQ截图20121118194509.png

Design a First-In-First-Out (FIFO) buffer that can store up to 8 data words received at port1 or port2 and deliver them in the same order at port3. Assume that each data word is 8-bit wide.

The external systems that provide data at port1 and port2 use the sender originated protocol and the system that requests data from port3 uses the receiver originated protocol.
Besides the system consisting of the data buffer, you should also design a test bench to simulate the three external systems. The first external system should read data from a file ”proj3A.dat” and apply it to your system at port1 using proper handshake. The second external system should read data from the file ”proj3B.dat” and apply it to port2
using handshake. The third external system will merely request data at port3 using proper handshake and copy it to its own register.
 

rberek

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So what is your question exactly?

r.b.
 

macgradywk

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I know how to do with one input port to one output port.
But how about two input ports?
I need a mux to choose from the two ports.
What would be the achitecture look like?QQ截图20121118225438.png
It is one input above
 

rberek

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How does the architecture above resolve the situation where the two DREADY signals are asserted at the same time?
 

macgradywk

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Not the same time. It should be clock 1, 2, 3, and clock 4 control FIFO
 

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