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design a CLB of the Spartan 6 family

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Herc11

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Designing CLB Spartan 6

Hi all,
I am trying to design a CLB of the Spartan 6 family at gate level and I am completely novice. I found out CLB’s structure from Xilinx but I want to know how each part is designed in transistor level especially look up table. Can anyone give me some piece of advice?
Many thanks,
Herc11
 

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