#### isamel85

##### Newbie level 6

I want to describe in VHDL a generator parallel 4 bits to serial 1 bit.

Indeed, at each clock edge (250 kHz), we take only one bit starting with the least significant bit (LSB).

Example:

Input = "0101" (over 4 bits)

So at first clock edge, output = '1' (LSB)

Second clock edge, output = '0'

Third clock edge, output = '1'

Fourth clock edge, output = '0' (MSB)

There's someone there who can help me?

And thank you