"derive_pll_clocks" doesn't create generated clocks for all outputs

[shaiko]

Hello,

In my Arria V design. I have a PLL with one input and 3 outputs. The input is 125 MHz. The outputs are as follows:

1. Output 0 - 125 MHz ( without phase shift - with properties identical to the input clock ).
2. Output 1 - 125 MHz ( without phase shift - with properties identical to the input clock ).
3. Output 2 - 25 MHz.

In Timequest I run "derive_pll_clocks" and look at the output of the command.

I was expecting to see 3 "create_generated_clock" - but I only see one. Only the output for the 3rd clock ( 25 MHz ) has a "create_generated_clock" command.

Why is that ?

 

[wwfeldman]

no idea, but i'll take a stab in the dark:

the optimize function in your system recognized outputs 1 and 2 as identical to the input
and did not do anything, as there was no "need", since it already exists.

is there a way to force the "compiler"(?) to ignore the "optimize" functions?

 

[shaiko]

That's also my suspicion...

 

[shaiko]

I think I found a solution:
https://www.intel.com/content/alter.../knowledge-base/solutions/rd03062013_146.html