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Depth of logical Circuit

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Richard29

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Hi all,

I sythesised (with Xilinx ISE) some complex logic circuit just consisting of AND and XOR gates and I am wondering if there is any
way I can identify in the post-sythese report the depth of the circuit in number of gates, ie. the number of logical
gates that make up the critical path.

Would be great if somebody could me help me out with this one!

Richard
 

There are no gates in FPGA (if you targeted FPGA, of course). Your circuit's logic equations were restructured and optimized for LUTs. So, the depth should measured in number of LUTs, not gates.
Correct me if I'm wrong.
 

After synthesising the code, check "view technology schematic" in xilinx ISE.. it will show the design logic implemented using LUT's(in your case)..

As Alexium said you wont be able to see the individual gates used in fpga.
 

if you open the synthesis report of XST, synthesis tool from Xilinx, you will find the number of levels of logic for the most critical path.

LUT is the primitive on which the logic levels will be computed. Based on the target device, LUT can be inferred as LUT1,LUT2,LUT3,LUT4,LUT5,LUT6.

LUT6 represents a 6-input function, where as LUT5 represents a 5-input function and so on
 

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