Richard29
Member level 1

Hi all,
I sythesised (with Xilinx ISE) some complex logic circuit just consisting of AND and XOR gates and I am wondering if there is any
way I can identify in the post-sythese report the depth of the circuit in number of gates, ie. the number of logical
gates that make up the critical path.
Would be great if somebody could me help me out with this one!
Richard
I sythesised (with Xilinx ISE) some complex logic circuit just consisting of AND and XOR gates and I am wondering if there is any
way I can identify in the post-sythese report the depth of the circuit in number of gates, ie. the number of logical
gates that make up the critical path.
Would be great if somebody could me help me out with this one!
Richard