Delta Sigma + Current steering DAC

[caosl]

Hi, all
In a delta sigma DAC, classical implementation is Digital interpolator -->Digital DSM -->Switch Cap dac & Filter --> active filter . Now, i want to replace the Switch Cap dac with current steering dac to save area and power consumption. The question is coming, how to resolve the jiter problem? The dac level is just 9.
All comments are welcome.

 

[mitrobge]

since jitter is usually modeled as noise, a randomization technique could maybe help...Data weighted averaging for example...I don't know if this is correct...

 

[st01liyp]

DEM would't work
I think the best way is: modeling
model the phase noise of pll, and make sure the
phase noise would't harm your dac.
if it does harm your dac, lower the phase noise or
quantization noise, or both.