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Delaying signal in Actel FPGA

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guybrush

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DELAY IN FPGA (SDF file)

Hi all.
I have to implement a 50 ns (nominal) pulse, 200 KHz using an FPGA that has a 2 MHz clock. I'm using an ACTEL fpga and the envirommental constraint are -25/+90°C.
Since it is imposible to produce a 50 ns pulse with a synchronous logic clocked @ 2MHz, I decide to use an AND gate in which one of the two input is a 200 KHz square wave and the second input is the same signal delayed. The simulation gives a 50 ns pulse in standard conditions.

The duration of the pulse is dependent on:

1) Voltage
2) Temperature
3) Process

Simulations show that the duration will be between 30 and 100, meeting my constraints.

You think this could be a good solution? Any suggestion?

Where can i find the description of the SDF file format ?

Thank you a lot.
 

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