delaying a square wave by 1us

[hioyo]

dear team,

I need to delay a suare wave by 1us( both rising and falling edge)
My expected I/P ,O/P waveform is given below,Can you suggest any method to do the same

Regards
hari

 

[KlausST]

Hi,

What about using an R-C circuit ... maybe followed by a schmitt trigger?

Klaus

 

[danadakk]

If you need something with a little more precision -

Done with single chip (most resources were not used, see right hand window) -

Used a PWM, triggered on both edges of input, and that in turn toggles T F-F
to produce output. So timing (w/o external xtal) is ~ +/- 1%, with xtal << .1%

I used 100 Khz waveform in for this example, could have been uHz. High limitation
is internal clock rates and how much precision you need in the delay, could do > 1
Mhz input freq.

Note onchip DDS and OR gate shown from onchip resources I used to test
its design, you would eliminate them if not needed.

In this particular example only 2 lines of code needed, start instructions to the PWM
and DDS. Obviously if you use many more of the chip resources you would be coding
as normal. Note however much of the digital and analog HW can be used codeless
(just start instructions for some) depending on what you need in overall design.

If your design is much more than just this delay here are some of the other resources
onchip -

What is max freq of input you need to handle ?


Regards, Dana.

 

[danadakk]

Obviously if you can tolerate 1 uS varying by 50% or more over T and V go
for the Schmidt solution with CMOS Schmidt. A OpAmp configured as Schmidt
would make things a lot better. But you still have RC tolerances to contend with.

Regards, Dana.

 

[cupoftea]

here is one way, and you can adapt this
its in LTspice

 

[danadakk]

One key question is how much variation in delay can you tolerate ?

Using Schmidt triggers and RC networks not based on clocks can yield some
pretty large variation over T and V and part accuracy. In fact the Schmidts have
virtually no design device characterization limits in their datasheets. Eg. curves
of threshold versus T, V, and of course the cap technology has to be carefully
chosen to get minimal delay sensitivity. Ceramics have a poor V dependence.
This may be inconsequential in Schmidt circuit since presumed V is regulated to
the Schmidt, but you still have to be careful picking one for T dependency.

Also of consideration is duty cycle, if thats important to you, and circuit variation
impact.

Capacitance Change & Variation In Capacitors - Voltage, Temperature &

The capacitor can be and is subjected to various electrical, mechanical, and environmental stresses. Find what causes the phenomena of capacitance variation.

www.electrocube.com

https://pdfserv.maximintegrated.com/en/an/TUT5527.pdf

Clocks in todays processors can be fairly accurate, as stated in post #3.

So you need to decide what accuracy you need over T and V and component variation
so your overall circuit works as intended.

Lastly on power up is your pulse source deterministic ? Or do you care if on initial
power up what the pulse delay circuit generates when input to it is wonky ? Post # 3
takes care of those issues as well.

if this is a one off design you can always substitute a pot in Schmidt RC circuit to trim
to desired value.


Regards, Dana.

 

[c_mitra]

dear team,

I need to delay a suare wave by 1us( both rising and falling edge)
My expected I/P ,O/P waveform is given below,Can you suggest any method to do the same
View attachment 172596
Regards
hari

Your expected I/P and O/P are unrealistic. You need to specify both the rise time and fall time.

An ideal square wave in reality looks more like trapezoidal. In addition you need to say the actual repeat frequency. From the drawing, the period looks more like 10us but that is a guess.

You also need to specify the margins on the 1us delay. Say 10%? or 1%?

The rise time and fall time will decide the speed of the components used to day the start and stop signal.

It will be good if you tell the pulse height also.

That essentially means everything you know about the pulse.

 

[hioyo]

Hi,

What about using an R-C circuit ... maybe followed by a schmitt trigger?

Klaus

Hi KlausST,

Thank you it is working.Instead of Schmitt trigger I used a Comparator from TI.

Regards
HAR

 

[barry]

Hi KlausST,

Thank you it is working.Instead of Schmitt trigger I used a Comparator from TI.

Regards
HAR

A comparator with positive feedback IS a Schmitt trigger.

 

[KlausST]

Hi,

My personal opinion:
* when I hear "schmitt trigger", then I think about a logic device with logic input and rather unprecise levels.
* when I hear "comparator with hysteresis", then I think about a circuit with analog input levels and rather precise threshold levels.

Examples:
* schmitt trigger: delay of a square wave ;-)
* comparator w. hyst: temperature controller

Klaus

 

[barry]

"In electronics, a Schmitt trigger is a comparator circuit with hysteresis..."

Schmitt trigger - Wikipedia

en.wikipedia.org

 

[KlausST]

Hi,

As written: it's just my personal opinion.

Klaus

 

[c_mitra]

"In electronics, a Schmitt trigger is a comparator circuit with hysteresis..."

This is true but the hysteresis refers to the voltage levels and not time.

For a perfect square wave input, I do not think you can make that distinction.
A Schmitt trigger is same as a comparator when the input is a square pulse.

To introduce the delay, you need to introduce a RC pair in the feedback.

 

[AMS012]

If you need a rough 1us delay, you could consider just putting a bunch of inverters to do the job.

If you need an accurate 1us delay that accomplishes some task for you like analog to digital conversion or some time based operation etc., you could do the standard way of delay locked loop as well. Example, 1us will be some fraction (say x%) of your period. Just put some delay programmable-inverters to roughly delay the waveform by 1us. Take the difference between the undelayed and delayed waveforms and detect its DC and compare it with x% of the Vdd (assuming proper settling of waveforms). Feed the error signal back to the delay cell to control the loop. Basically, the standard delay locked loop would do.

--- Updated Nov 3, 2021 ---

Adding RC to get the delay is a good idea, but maybe it is not as good for phase noise if it is a concern, depending the input frequency and the delay required.

 

[c_mitra]

If you need a rough 1us delay, you could consider just putting a bunch of inverters to do the job.

The simplest solution is often the best even for demanding applications. Unfortunately the original poster has not yet told us the application, the motivation and the specifications related to the task in hand.

Personally I believe that designs that depend critically on one parameter (say absolute value of the delay) - unless that is the primary objective- not good designs.

 

[barry]

If you need a rough 1us delay, you could consider just putting a bunch of inverters to do the job.

A typical old-school 74LS04 inverter has about 15nS propagation delay. So you're proposing using 66 inverters?

As c-mitra implies, without more definition from the OP it's a waste of everybody's time to speculate on a "proper" solution.

 

[FvM]

Although we miss an accuracy specification, the OP stated that a RC delay circuit followed by a comparator serves his requirements. This sounds reasonable, we can easily achieve a delay accuracy of e.g. 5 to 10 % without adjustment.

 

[barry]

This is true but the hysteresis refers to the voltage levels and not time.

For a perfect square wave input, I do not think you can make that distinction.
A Schmitt trigger is same as a comparator when the input is a square pulse.

To introduce the delay, you need to introduce a RC pair in the feedback.

The hysteresis prevents the comparator from generating a noisy output from a slow (RC) signal on the input. The delay comes from the RC on the input, not in the feedback.