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delayed generated clock

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tech9412

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In my design master clock is clk and divide by 2 clock is clk_div2 which is generated through clk.
One more clock is generated which is one clock period delayed w.r.t clk and divide by 2 also.How to give constrain for this delayed clock in DC.
 

shobhit

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Re: delayed generated

While creating the generated clock there is an option edges there you can specify the edges as 3 5 7 which means as follows:
1st rise edge of generated clock is 3rd edge of master clock
next fall edge of generated clock is 5th edge of master clock
next rise edge of generated clock is 7th edge of master clock
after this the pattern will be repeated..............

In this way you will create a generated clock with a delay of 1 period of master clock ana also a divided version.

Note: Start counting the edges of master clock with with 1st edge as '1' and then 2,3,4 and so on



hope this helps
 

ljxpjpjljx

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all of your generated clock will have cross-domain signal?
 

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