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Delay statement and clock generation in Verilog

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ds18s20

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Hi everyone,

Since we know that FPGA in general CAN NOT generate clock, but instead a clock must be fed into them from another source.

Then why is there # xx delay statement in Verilog or to put it another way - why are there so many examples of how we can "generate" a clock with:

Code:
@always #10 q= ~q

That never made sense to me? How would the FPGA know what the length of 10 time units is and where do the time units come from in the first place? Is this some evil compiler thing or does it exist PURELY SYNTHENICALLY only within the software environment for the purpose of testing and simulation?

And even if this is synthetic concept, how does one tell the compiler what one time unit is and where is the counting kept for this to work? Is it all transparent to the Quartus2 user?

In my mind I see serious conceptual problems when I encounter “assign # xx” statements.

Thanks much
~B
 

Old Nick

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It's necessary for a test bench though.
 

aajizattari

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Well!

This is indeed for test and simulation purposes ...
so that you can test your design yourself in the Software itself ....


and see if your design meets timing requirements




This thing is not at all synthesizeable .... at all

As for the time units you will have noticed they are specified in form of 'timescale ' to the tool we are using (I use Xilinx ISE )


You are right in that it is purely within software .....
That would indeed be a magic if a black box of hardware knows about seconds and nanosecs by itself
 

pankajrangaree1

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u r question is nice,but dnt give clk signal in the ckt,instead introduce some combinational ckt which is having delay.
 

manish12

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Delay statement and clock generation in HDL i think

it for designer to get some hint about signal and delayed signal due to path,

so that he will at least think in that direction .
 

sp

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verification required those delay a lot...

when creating behavioral models... when doing testbench.

but when you are FPGA user, we won't use that as those delay statement is unsynthesizable...
 

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