delay(several us) for PWM signal

[robertzhan]

Dear all,

I'd like to make a routine to have a delay for PWM signal, about several microsecond, just like the hold on function. But it emerges the following error:

Error: VHDL error at soft_switching.vhd(70): can't infer register for signal "p01:counter[0]" because signal does not hold its value outside clock edge

I don't know why. Hope for your suggestions.
If it can't do like this, how to make a routine to realize the function of several us delay for the input PWM signal.

Thank you in advance.




LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;


-- Entity Declaration

ENTITY soft_switching IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
pwm : IN STD_LOGIC;
ilt : IN STD_LOGIC;
clk : IN STD_LOGIC;
pwm_delay : OUT STD_LOGIC;
tab : OUT STD_LOGIC;
tl : OUT STD_LOGIC
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

END soft_switching;


-- Architecture Body

ARCHITECTURE soft_switching_architecture OF soft_switching IS

--SIGNAL counter : integer := 0;
SIGNAL flag : bit;
SIGNAL pwm_temp : STD_LOGIC;

BEGIN

p01: process(clk,pwm) is

variable counter : integer :=0;

begin
case pwm is
when '1' =>
loop1: loop
if (clk'event AND clk = '1' AND clk'last_value = '0') then
counter := counter + 1;
end if;
exit loop1 when counter = 20;
END loop loop1;
pwm_delay <= '1';
counter := 0;

when '0' =>
loop2: loop
if (clk'event AND clk = '1' AND clk'last_value = '0') then
counter := counter + 1;
end if;
exit loop2 when counter = 20;
END loop loop2;
pwm_delay <= '0';
counter := 0;
end case;

end process p01;

END soft_switching_architecture;

 

[vishwa]

Hi

In your program, you tried to synchronize some process with clock. But you have done it inside the process. It doesn't work.

If you want synchronize the design with a clock, you should check the clock trigger at the beginning of the program.

And also the loop statement doesn't work, because it cannot be implemented in hardware.

You can change the program like this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY soft_switching IS
PORT
(
pwm : IN STD_LOGIC;
ilt : IN STD_LOGIC;
clk : IN STD_LOGIC;
pwm_delay : OUT STD_LOGIC;
tab : OUT STD_LOGIC;
tl : OUT STD_LOGIC
);

END soft_switching;


-- Architecture Body

ARCHITECTURE soft_switching_architecture OF soft_switching IS

SIGNAL flag : bit;
SIGNAL pwm_temp : STD_LOGIC;
signal counter : std_logic_vector(4 downto 0) ;
BEGIN

p01: process(clk,pwm) is
begin

if (clk'event AND clk = '1' AND clk'last_value = '0') then

if (counter="10100") then

if pwm='1' then
pwm_delay <= '1';
else
pwm_delay <= '0';
end if;

counter <="00000";

else
counter <= counter + 1;
end if;

end if;

end process p01;

END soft_switching_architecture;



In fact, I could not catch what you are planning to do. But this is the right modification for the program given by you.

For the counter variable, you can change the length of the vector based on your requirement.


Regards,
Vishwa

 

[robertzhan]

Dear Vishwa
Thank you for your kind help. However, it still doesn't meet my request. The timing edge is not very precise and pwm signal after delay has been affected. The attachment gives the figure to show my aim. Could you tell me how to modify the routine to ensure the delay time and the pwm after sigal to be less influenced.

Thank you very much.

Robert Zhan

 

[vishwa]

Hi

Do you want to generate the replica of the PWM signal at the output after some delay?

I could understand that you want to generate the PWM_delay as the delayed version of PWM signal. Am I right. If so, let me know. I can give you a better solution.

Explain clearly.


Regards,
Vishwa

 

[robertzhan]

Dear Vishwa,
Thank you for your kind help.
yes, I want the replica of the PWM signal at the output after some delay (several microsecond), it's could also deemed as the delayed version of the pwm signal.

Thanks.

Regards

Robert Zhan

 

[vishwa]

Hi

To get the delayed version of the PWM signal, you can use the following program.


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY soft_switching IS
PORT
(
pwm : IN STD_LOGIC;
ilt : IN STD_LOGIC;
clk : IN STD_LOGIC;
pwm_delay : OUT STD_LOGIC;
tab : OUT STD_LOGIC;
tl : OUT STD_LOGIC
);

END soft_switching;


-- Architecture Body

ARCHITECTURE soft_switching_architecture OF soft_switching IS
signal clk_divider: std_logic_vector(7 downto 0);
signal counter : std_logic_vector(4 downto 0) ;
signal 2bit_reg: std_logic_vector( 1 downto 0);
BEGIN

po1: process(clk)
begin
if (clk 'event and clk='1') then
clk_divider <= clk_divider +1;
end if;
end process p01;

p02: process(clk_divider(7),pwm) is
begin

if (clk_divider(7) 'event AND clk_divider(7) = '1') then

if (counter="00010100") then

pwm_delay <=2bit_reg(1);
2bit_reg(1) <=2bit_reg(0);
counter <="00000000";

else
counter <= counter + 1;
end if;

2bit_reg(0) <= pwm;

end if;

end process p02;

END soft_switching_architecture;

In this program, last value of pwm is stored in 2bit_reg(0). After some delay, it can change the output. To change the delay as per your requirement, you can change either clk_divider length or counter length or both.

If you change clk_divider length, then you have to chenge the process sensitivity list with new clk_divider bit. Here it acts as internal clock with low frequency(higher delay).

I think this modification is enough to get the delayed version of PWM. But still I could not get what is the use of the output signals tab and tl.


Ok. All the best.

Regards,
Vishwa

 

[echo47]

Another way to delay a signal is to pass it through a long shift register. That allows multiple transitions during the delay time. If your device has RAM available, then you can configure it as a really long shift register.

 

[robertzhan]

Dear Vishwa and echo47
Sorry to express my appreciation so late since I'm on business last few days.
Thank you for your positive suggestions, especially Vishwa's insistent help and support to make my problem solved more quickly than expectation.

All the best.

Best wishes,

Robert Zhan