Delay modeling in Test Bench

[YuLongHuang]

HI~!
I have problems when I try to model the delay in Test bench.

I'd like to model the behavior of Interconnection network, or network on Chip. The latency for each packet is different and depends on the distance of destination. My design doesn't contains the router but I still have to consider this effect in Test bench.


My problems is that:
How do I write the delay behavior such that the fulfill the following demands ?
1. Every clock, there will be one packet to be assigned to other router.
2. Delay is not constant and usually larger than one clock period.


Currently, I use the FIFO-like for allocation of packets. For packets transmitted to that router is first stored in the FIFO and later the FIFO will fetch the data and assign to the router.
However, I still can't model the behavior correctly for following simple example (it's still uncorrect)

always @ (posedge clock) begin
in <= {$random} % 16;

t <= in*10;
#t buff[wptr] <= in.
wptr <= wptr + 1;
end

I have google the related concept of inertial and transport delay. However, question is still unsolved.
1. variable of "in" must be previous value and that's transport delay.
2. variable of "wptr" must be newest value and that 's inertial delay.
3. once the "t" is larger than clock period, the always block will be postponed until the last statement is finished.


Does anyone have other ideas ?
Thanks.

Best Regards.

 

[aVi3467]

Have you considered using wait statement instead of the assignment delay?

wait (expression) statement

 

[YuLongHuang]

Have you considered using wait statement instead of the assignment delay?

wait (expression) statement

Un...I have never thought about that.
It seems irrelevant at first sight.