melpinto
Newbie level 1
Designing a DLL done in CS inverter with symmetric load for 32 phases. Frequency input range is 100Mhz to 208Mhz.
Locking is not occurring as delay is remaining constant. Also, duty cycle is reducing in each stage as negative edge is not delaying fast as positive edge.
Design done in Cadence Spectre tool in 90nm. How to solve these issues?
Locking is not occurring as delay is remaining constant. Also, duty cycle is reducing in each stage as negative edge is not delaying fast as positive edge.
Design done in Cadence Spectre tool in 90nm. How to solve these issues?