delay in verilog program

[MRFGUY]

I try to write the finite state verilog program that need to wait sometime in current state before go to next state. I used

example : repeat (10) @(posedge clk);
But error appear like this:

ERROR:Xst:850 - a.v line 32: Unsupported Event Control Statement.

Is there any other method to do.

My ver is xilinx 5.2.

Thanks

 

[msv91280]

hi

i cant understand your question ,explain properly or send the FSM code mentioning were you want delay.

or else try this:
If u want the delay before validating the next state use delay(ie #10) before the particular case statement
ie:
case()
#10 s1:if (present stste==1'b0)
nextstate=s2

regards

 

[MRFGUY]

How do I stay at state BS for some time before going on to state DS in next clock.

`define AS 2'b00
`define BS 2'b01
`define DS 2'b10

module vtest(clk, rst, x, A, B, C);

input clk, rst, x;
output A, B, C;

reg [1:0] state, nstate;
reg A, B, C;

always @(posedge clk)
begin
if (rst)
state <=`AS;
else state<=nstate;

end

always @(x, state)
begin

case(state)

`AS :begin
if (x==0) nstate = `AS;
else nstate = `BS;
end

`BS :begin
nstate = `DS;
end


`DS :begin
if (x==1) nstate = `DS;
else nstate = `AS;
end


default : nstate = `AS;
endcase
end

always @(state)

begin
case (state)
`AS : begin A=0; B=0; C=1; end
`BS : begin A=0; B=1; C=0; end
`DS : begin A=1; B=0; C=0; end

default : begin A=0; B=0; C=1; end
endcase

end

endmodule

 

[nand_gates]

Checkout the following code...
Hope this helps!
In state BS it will wait for 10 clock cycles befor it goes to state DS!

`define AS 2'b00
`define BS 2'b01
`define DS 2'b10

module vtest(clk, rst, x, A, B, C);
   
   input clk, rst, x;
   output A, B, C;
   
   reg [1:0] state, nstate;
   reg       A, B, C;
   reg [3:0] cnt, cnt_nx;
   
   always @(posedge clk) begin
      if (rst) begin
         state <= `AS;
         cnt <= 0;
      end else begin
         state <= nstate;
         cnt <= cnt_nx;
      end
   end

   always @(x, state) begin
      case(state)
        `AS :begin
           if (x==0) 
             nstate = `AS;
           else 
             nstate = `BS;
        end
        
        `BS :begin
           if (cnt == 0 )
             nstate = `DS;
           else
             nstate = `BS;
        end
        
        
        `DS :begin
           if (x==1) 
             nstate = `DS;
           else 
             nstate = `AS;
        end
        
        default : nstate = `AS;
      endcase
   end // always @ (x, state)
   
   // Delay counter
   always @(state or cnt )begin
      cnt_nx = cnt;
      case (state)
        `AS : cnt_nx = 10;
        `BS : cnt_nx = cnt -1;
        `DS : cnt_nx = 10;
      endcase
   end
   
   always @(state)begin
      case (state)
        `AS : begin A=0; B=0; C=1; end
        `BS : begin A=0; B=1; C=0; end
        `DS : begin A=1; B=0; C=0; end
        default : begin A=0; B=0; C=1; end
      endcase
   end
endmodule

 

[yakroo]

What use software verilog?