Definition of Generated clock in the following scenario ?

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eda_rattle

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Hi,

Two definitions given for two stage generated clocks ? Which one seems to be a better definition & WHY ?

How does CTS tool build the clock tree DIFFERENTLY in two cases ?

Definition 1 :

create_clock -name SOURCE_CLK1 -period 1.0 [get_ports clk]
create_generated_clock -source [get_ports clk] -name GENCLK_1 -divide_by 2 [get_pins FF1/q]
create_generated_clock -source [get_pins FF1/q] -name GENCLK_2 -divide_by 2 [get_pins FF2/q]

Definition 2 :

create_clock -name SOURCE_CLK1 -period 1.0 [get_ports clk]
create_generated_clock -source [get_ports clk] -name GENCLK_1 -divide_by 2 [get_pins FF1/q]
create_generated_clock -source [get_ports clk] -name GENCLK_2 -divide_by 4 [get_pins FF2/q]

Regards,
eda_rattle
 

Def 1 is right. Just check out the create_gen_clock command on solvnet..
 

Check out what -source means from the same link. It says the driving element should be specified here.
 

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