define the verilog netlist model

[siva_7517]

Below is the verilog coding and verilog netlist for simple flip flop

***************************************************************************************************************************
module ff (clk, rst, d, q);
input clk, rst, d;
output q;

reg q;

always @(posedge clk)
begin
if(rst)
q = 0;
else
q = d;
end

endmodule





***************************************************************************************************************************
// Generated by ac_shell v5.14-s078 on Mon Jan 23 12:00:55 MYT 2006.

// Restrictions concerning the use of Ambit BuildGates are covered in the
// license agreement. Distribution to third party EDA vendors is
// strictly prohibited.


module ff(clk, rst, d, q);

input clk;
input rst;
input d;
output q;




DFFTRX1 q_reg(.D(d), .CK(clk), .RN(n_3), .Q(q));
INVX1 i_8(.A(rst), .Y(n_3));
endmodule

*****************************************************************************************************************************[

above is the verilog netlist after optimize with artisan library. i am using .alf file.Eventually, when i import to icfb it has statement :


Verilog defination for module DFFTRX1 was not found. using lib 'silterra18' cell 'DFFTRX1' view 'symbol' as its symbol


Verilog defination for module INVX1 was not found. using lib 'silterra18' cell 'INVX1' view 'symbol' as its symbol

So, because this error i cannot use the verilog xl to do gate level simulation. How can i define the module?

 

[tarkyss]

you must import symbol view too

 

[siva_7517]

How do i import the symbol

 

[siva_7517]

Can u give me some guidelines on how to import the symbol view.

 

[sunrise]

If you only want to run gate level simulation by verilog-xl, it's not necessary to import netlist to icfb. You can run verilog-xl directly. For example,

verilog $verilog_netlist -v $verilog_library -y $verilog_library_path

$verilog_library can be found in which library installed.