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.def file- soc encounter - help needed

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ksrinivasan

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.def file- soc encounter

Friends

This is a question with respect to soc encounter
There is a option of including .def file while importing vhdl/verilog RTL in the physical tab
My PDK does not contain this file,but the synthesis completed without any error
Can someone tell me what is the importance of this file
Can i work without it in this tool

Srinivasan
 

iwpia50s

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.def file- soc encounter

The DEF file contains cell placement. If all you've done is synthesize RTL you do not need DEF.
 

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