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decreasing bottom plate parasitics in MOM capacitors

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analogLow

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Hi,

I have modeled my mom cap and I need to reduce the bottom plate capacitance (Cbottom) further.

Is it possible to reduce the Cbottom by placing an NWELL or DEEP NWELL (or something) under the cap?

thanks,
analogLow:-D
 

Almost any oxide cut under the cap will -increase- bottom
plate capacitance, by reducing Tox(). However in a non-
planarized technology you might be able to -increase-
the Tox() by surrounding the cap with rings of poly and
metal, making the spin-on-glass "pond up". But then you
would pick up these fringing capacitances.

A bottom plate that is electrically distinct, but co-driven,
would not reduce capacitance per se but will minimize the
charge transferred and leakage. Kinda like triax cable is
used for low leakage DC measurements. Not likely a good
plan for RF, but OK for stuff like analog sampling.
 

Thanks >(. I am not clear what you mean by oxide cut. I mean the caps I am using are using are just metal / vertical parallel plates with no transistors underneath.

analogLow


Almost any oxide cut under the cap will -increase- bottom
plate capacitance, by reducing Tox(). However in a non-
planarized technology you might be able to -increase-
the Tox() by surrounding the cap with rings of poly and
metal, making the spin-on-glass "pond up". But then you
would pick up these fringing capacitances.

A bottom plate that is electrically distinct, but co-driven,
would not reduce capacitance per se but will minimize the
charge transferred and leakage. Kinda like triax cable is
used for low leakage DC measurements. Not likely a good
plan for RF, but OK for stuff like analog sampling.
 

By placing Nwell or a D-Nwell the capacitance can't be reduced, i think the only way is to use a higher level metal as the bottom plate....
 

Thanks >(. I am not clear what you mean by oxide cut.

NWell and deep N+ implants are most likely hard-
masked by etching the original field oxide. The final
oxide thickness there will be less than undisturbed
(P-) areas.
 

There will be always some parasitic cap. You can't reduce it effectively. BUT you can choose to which node it will be parasitic (against ground or power or something else). Choose wisely...
 

thanks for all the tips ... in the end, I used higher metals and min. spacing and lots of vias. know i have much less bottom plate cap

-analogLow
 

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