Decoupling capacitor for RF power amplifier

[Mabrok]

Hi,

I can not see any effect on the simulation results after adding decoupling capacitor. Even when i tune the capacitance value, I can not see any effect. Is this normal?

 

[KlausST]

Hi,

It depends on how realistic your simulation is.

Every battery has different parameters. Series resistance, series impedance depending on frequency and load current and aging.
It depends on manufacturer, type, size, chemistry....

When I see it correctly, then there is an ideal capacitor connected to an ideal battery with ideal wiring.
But usually there is a real battery with real wiring .... causing impedance. And to compensate for this there should be a capacitor placed on the PCB close to the load.

Klaus

 

[Dominik Przyborowski]

You are shorting these caps by ideal voltage sources. No behavior difference is expected.

 

[BigBoss]

If you wanna see the effect of the capacitor, use s-parameters or equivalent modeled circuit of the capacitor.
You will see how a capacitor effects the PA.

 

[danadakk]

To emphasize what KlausST said if you connect ANY component in parallel
with true V source, the V source controls the V of that branch its connected
to, no matter what Z is attached to that branch. Except of course in the limits,
like a short.

Same is true if you connect ANY component in series with a current source
the current source controls the current in that branch. Except of course in the limits,
like an open.

Only with sources with non ideal parameters, series R > 0 in case of V source,
series R < infinity for current source, will be affected by the addition of other
impedance's.


Regards, Dana.

 

[Mabrok]

If you wanna see the effect of the capacitor, use s-parameters or equivalent modeled circuit of the capacitor.
You will see how a capacitor effects the PA.

@BigBoss How to choose the right value of the capacitor? Based on what? Are there mathematical equation to calculate the value?

 

[BigBoss]

@BigBoss How to choose the right value of the capacitor? Based on what? Are there mathematical equation to calculate the value?

There should practically be few capacitors connected in parallel there.
-High value for low frequencies ( DC to few hundred kHz and uF range )
-Medium value for medium frequencies ( nF or few hundred pF range)
-Low value for high frequencies.( pF range )

Because every capacitor has a highest admissible frequency limit due to ESR.Therefore we use few capacitors to cover overall frequency band.
But in simulations, the practical effects can be seen as if the capacitors are very well modeled or used with their equivalent circuits.
The most important parameter is ESR for capacitor then series inductance ( for high frequency capacitors ) plus parasitic capacitors at each terminal to GND.
However there isn't any empirical formulae for them. You should simulate with their equivalent circuits or s-parameters ( s-parameters can cause some troubles in simulations that's why I prefer using equivalent RLCk circuit ) then you have to decide which type and what value of capacitor must be used by observing circuit metrics.( Noise,Non-linearity,Output Power, Band Flatness,Reflections etc. )

 

[Mabrok]

There should practically be few capacitors connected in parallel there.
-High value for low frequencies ( DC to few hundred kHz and uF range )
-Medium value for medium frequencies ( nF or few hundred pF range)
-Low value for high frequencies.( pF range )

Because every capacitor has a highest admissible frequency limit due to ESR.Therefore we use few capacitors to cover overall frequency band.
But in simulations, the practical effects can be seen as if the capacitors are very well modeled or used with their equivalent circuits.
The most important parameter is ESR for capacitor then series inductance ( for high frequency capacitors ) plus parasitic capacitors at each terminal to GND.
However there isn't any empirical formulae for them. You should simulate with their equivalent circuits or s-parameters ( s-parameters can cause some troubles in simulations that's why I prefer using equivalent RLCk circuit ) then you have to decide which type and what value of capacitor must be used by observing circuit metrics.( Noise,Non-linearity,Output Power, Band Flatness,Reflections etc. )
View attachment 163445

Where I can find equivalent RLCk circuit of the capacitor? Can be used in ADS simulation?

 

[BigBoss]

Where I can find equivalent RLCk circuit of the capacitor? Can be used in ADS simulation?

You should request from the vendor or download Design Kit of the vendor and install it. The Design Kit will include all necessary parameters of the component.For instance..( small ceramic capacitors only )

Keysight PathWave Advanced Design System | EDA Library | Murata Manufacturing Co., Ltd.

Electronic component data of Murata Manufacturing compatible with Keysight PathWave Advanced Design System is provided.

www.murata.com

For other type of capacitors, you should consult to the associated vendor.

 

[stenzer]

Hi,

Where I can find equivalent RLCk circuit of the capacitor? Can be used in ADS simulation?

the simulation tool KSIM [1] provided by KEMET is pretty handy to have a look on the impedance and ESR of different capacitor types provided by KEMET. The tool provides also other kind of insigths like "Capacitance vs Bias Voltage", "Capacitance and Inductance". etc..

[1] https://ksim.kemet.com/

BR

 

[Mabrok]

There should practically be few capacitors connected in parallel there.
-High value for low frequencies ( DC to few hundred kHz and uF range )
-Medium value for medium frequencies ( nF or few hundred pF range)
-Low value for high frequencies.( pF range )

Because every capacitor has a highest admissible frequency limit due to ESR.Therefore we use few capacitors to cover overall frequency band.
But in simulations, the practical effects can be seen as if the capacitors are very well modeled or used with their equivalent circuits.
The most important parameter is ESR for capacitor then series inductance ( for high frequency capacitors ) plus parasitic capacitors at each terminal to GND.
However there isn't any empirical formulae for them. You should simulate with their equivalent circuits or s-parameters ( s-parameters can cause some troubles in simulations that's why I prefer using equivalent RLCk circuit ) then you have to decide which type and what value of capacitor must be used by observing circuit metrics.( Noise,Non-linearity,Output Power, Band Flatness,Reflections etc. )
View attachment 163445

How if I used one piece for each power supply with 10 PF capacitance? As I could not find the RLC circuit for the component? Only available S2P file?

 

[stenzer]

Hi,

maybe the library from TDK [1] is what are you looking for.

[1] https://product.tdk.com/info/en/technicalsupport/tvcl/ads/index.html

BR

 

[Mabrok]

There should practically be few capacitors connected in parallel there.
-High value for low frequencies ( DC to few hundred kHz and uF range )
-Medium value for medium frequencies ( nF or few hundred pF range)
-Low value for high frequencies.( pF range )

Because every capacitor has a highest admissible frequency limit due to ESR.Therefore we use few capacitors to cover overall frequency band.
But in simulations, the practical effects can be seen as if the capacitors are very well modeled or used with their equivalent circuits.
The most important parameter is ESR for capacitor then series inductance ( for high frequency capacitors ) plus parasitic capacitors at each terminal to GND.
However there isn't any empirical formulae for them. You should simulate with their equivalent circuits or s-parameters ( s-parameters can cause some troubles in simulations that's why I prefer using equivalent RLCk circuit ) then you have to decide which type and what value of capacitor must be used by observing circuit metrics.( Noise,Non-linearity,Output Power, Band Flatness,Reflections etc. )
View attachment 163445

How to determine the number of required caps? Are there any equations?

 

[stenzer]

Hi,

usually you would estimate your required capacitance value according to your expected undesired frequencies by Z = 1/(2 . pi . f. C). To get rid of this frequencies a low impedance Z is desired. But at high frequencies capacitors may already act like an inductor (increasing impedance with increasing frequency). Larger valued capacitors start “earlier“ (at lower frequencies) to act as inductor than caps with a low value. Thus serveral caps are used in parallel to cover a desried frequency band. The final number depends on your frequency band as well on the chosen capacitor types/values.

Have a look at the ksim simulator I linked at post #10. There you can have a direct look at the impedance vs. frequency behaviour for individual caps. It is also possible to export the corresponding Spice and S2P file. Or you have a look at the datasheet of other manufacturer.

BR

 

[Mabrok]

Hi,

usually you would estimate your required capacitance value according to your expected undesired frequencies by Z = 1/(2 . pi . f. C). To get rid of this frequencies a low impedance Z is desired. But at high frequencies capacitors may already act like an inductor (increasing impedance with increasing frequency). Larger valued capacitors start “earlier“ (at lower frequencies) to act as inductor than caps with a low value. Thus serveral caps are used in parallel to cover a desried frequency band. The final number depends on your frequency band as well on the chosen capacitor types/values.

Have a look at the ksim simulator I linked at post #10. There you can have a direct look at the impedance vs. frequency behaviour for individual caps. It is also possible to export the corresponding Spice and S2P file. Or you have a look at the datasheet of other manufacturer.

BR

"undesired frequencies", in my case are the harmonics 2nd, and 3rd harmonics. How about the relationship between these caps and the desired frequencies. Can you please explain more as I still have no clear vision about selection of these caps? What will happen if don't select the values and numbers of caps properly?

 

[stenzer]

Hi,

from your inital post it looks like you are using the t-junction to bias a jfet transistor. Thus I assume the t-junction has been designed in a way that the voltage source connected to the center connection represents a high impedance seen from the t-junction. Thus its purpos is to provide a dc voltage whereas RF signals towards the source should be blocked. Consequently also your frequency band of interest (or CF) should be considered as undisired at the connection point of your voltage source, as a stable dc biase voltage is desired. Further, you do not want to short your information signal/frequencies itself, only that part which has been insufficient blocked by the t-junzzion.

BR

 

[Mabrok]

Hi,

usually you would estimate your required capacitance value according to your expected undesired frequencies by Z = 1/(2 . pi . f. C). To get rid of this frequencies a low impedance Z is desired. But at high frequencies capacitors may already act like an inductor (increasing impedance with increasing frequency). Larger valued capacitors start “earlier“ (at lower frequencies) to act as inductor than caps with a low value. Thus serveral caps are used in parallel to cover a desried frequency band. The final number depends on your frequency band as well on the chosen capacitor types/values.

Have a look at the ksim simulator I linked at post #10. There you can have a direct look at the impedance vs. frequency behaviour for individual caps. It is also possible to export the corresponding Spice and S2P file. Or you have a look at the datasheet of other manufacturer.

BR

@stenzer How much this low Z should be? specific range or value?

 

[Mabrok]

There should practically be few capacitors connected in parallel there.
-High value for low frequencies ( DC to few hundred kHz and uF range )
-Medium value for medium frequencies ( nF or few hundred pF range)
-Low value for high frequencies.( pF range )

Because every capacitor has a highest admissible frequency limit due to ESR.Therefore we use few capacitors to cover overall frequency band.
But in simulations, the practical effects can be seen as if the capacitors are very well modeled or used with their equivalent circuits.
The most important parameter is ESR for capacitor then series inductance ( for high frequency capacitors ) plus parasitic capacitors at each terminal to GND.
However there isn't any empirical formulae for them. You should simulate with their equivalent circuits or s-parameters ( s-parameters can cause some troubles in simulations that's why I prefer using equivalent RLCk circuit ) then you have to decide which type and what value of capacitor must be used by observing circuit metrics.( Noise,Non-linearity,Output Power, Band Flatness,Reflections etc. )
View attachment 163445

Regarding this, which frequencies should I consider while I am selecting the caps? Let's say, i want to measure s-paramrter over 2 to 6 GHz. My target frequency band is 3.4 to 3.6 GHz. So, in this case which freqiency should i consider in terms of ESL & ESR? Is it all frequrncies from 2 to 6 GHz or only 3.4-3.6 GHz band of interset? In other words, what are the frequency of noise that we need to suppres using decoupling caps or how to be determined? Thank you

 

[Mabrok]

If you wanna see the effect of the capacitor, use s-parameters or equivalent modeled circuit of the capacitor.
You will see how a capacitor effects the PA.

How if some of these components does not have model especially through hole caps? As I use combination of smd and through hole caps

 

[danadakk]

Have you got a VNA you can eval caps you are using ?

Low cost - https://www.ebay.com/sch/i.html?_from=R40&_trksid=p2380057.m570.l1313&_nkw=nano+vna&_sacat=0

Or use a model for an equaivalent cap that has a model....for a rough idea of what performance look like.


Regards, Dana.