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decoder for bigger memories

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dll_fpga

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how to write the decoder for bigger memories in the range of 100k....please give the clue for the RTL without using any for loop constructs

---------- Post added at 21:47 ---------- Previous post was at 21:18 ----------

since 2^address lines decoder is difficult to program......and it will face timing issues
how to write the decoder for bigger memories in the range of 100k....please give the clue for the RTL without using any for loop constructs
 

blooz

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how to write the decoder for bigger memories in the range of 100k....please give the clue for the RTL without using any for loop constructs

---------- Post added at 21:47 ---------- Previous post was at 21:18 ----------

since 2^address lines decoder is difficult to program......and it will face timing issues

Hi dll_fpga ,

Yes avoiding for loops is good practice this case ,And there is of course a need for low latency memory.
CPU Data caches use another type of decoder called sum address Decoder where A significant delay and area improvement is achieved .Many Decoders use Predecoding


h**p://en.wikipedia.org/wiki/Sum_addressed_decoder

---------- Post added at 23:53 ---------- Previous post was at 23:13 ----------

Lyon-Schediwy decoder is an improved decoder that can be fabricated in significantly less silicon area than existing NOR gate decoder arrays and is faster than existing NOR gate decoder arrays.
 
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dll_fpga

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thanks blooz.....ure welcomed for more info........

Hi dll_fpga ,

Yes avoiding for loops is good practice this case ,And there is of course a need for low latency memory.
CPU Data caches use another type of decoder called sum address Decoder where A significant delay and area improvement is achieved .Many Decoders use Predecoding


h**p://en.wikipedia.org/wiki/Sum_addressed_decoder

---------- Post added at 23:53 ---------- Previous post was at 23:13 ----------

Lyon-Schediwy decoder is an improved decoder that can be fabricated in significantly less silicon area than existing NOR gate decoder arrays and is faster than existing NOR gate decoder arrays.
 

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