decimation filter design

[triump.ar]

i hv to design decimation filter in which it consists of three stages the first stage of cic filter and followed by two stages of half band filter...i know the basics of both but i m not able to implement it using vhdl..i have some problmes
1. how to use delay in vhdl.....(we r using registers but how its gonna work)
2. the filter coefficients
3. how to decimate???

 

[cafukarfoo]

1. how to use delay in vhdl.....(we r using registers but how its gonna work)
For the CIC example,
let say ur decimation factor = 32

so you will have a 5 bit counter. When this counter reach 32, you will output an output sample.
That mean you will only get 1 output sample for each 32 clock cycle. Which mean you had decimate the sample by factor of 32

2. the filter coefficients
i think u can use 2 option:
a. design the filter using matlab. matlab will give you the coefficient.
b. you can use the formula to count it. for example a low pass filter,
the frequency response h= sin(xn)/n*pi. when x = 0,pi/4,/pi/2,3*pi/4

3. how to decimate???
if u decimate by 2, that mean you generate a output sample after 2 input sample.
if u decimate by 32, that mean you generate a output sample after 32 input sample.

please click "Help" button if i did help. thanks.