Dealing with signed operations in verilog.. help needed

[hallovipin]

Hi friends

module (operand_1, operand_2, sum );

input [7:0] operand_1, operand_2;
output reg [8:0] sum;
reg [8:0] difference;

initial begin
difference=0;
sum=0;
end



always @(posedge clk) begin

difference = operand_1-operand_2;
sum = sum + difference;

end


Now the question is if difference is -ve (2-3) at some point what will happen to sum. whether sum will recognize it and decrease or it will not treat difference as 2's complement and will simply increase

 

[FvM]

It should be noted, that Verilog also has a signed data type. But in case of the add and sub operation, it doesn't change anything. The difference between unsigned and two's complement signed is only in the interpretation of the result, the bitvector is the same. You may want to verify this by pencil and paper method.

In some cases, saturation logic may be wanted with arithmetic operations. But it's not provided by the basic add and sum operators.