Dealing with Ethernet in Router Design

I'm working on a router
I am going to implement an router interface in my design using quartus (my design is based on FPGA)
now I want to parsing it's packages....
Does the interface do it itself?
if not what's the start/stop bits or signal pattern?
I've design a start stop bit detector and know I want it's pattern
the detector has CLK and Data_Serial_In and a given pattern for start and stop....when the input register detect the start or stop it will send a signal or set a flag....
but I want to know:
1.is there any start stop bits pattern?
2.does Ethernet use both start and stop?

thank for your help

Added after 15 minutes:

I've found sth here at CISCO systems:
https://www.cisco.com/en/US/docs/internetworking/technology/handbook/Ethernet.html
actually I want to implement the Ethernet Interface with IP and Mega Functions but what are thier outputs?
I don't want to consider the Ehternet detail I want to use
an pattern as start bit for example just using SOF field
and if needed I'll use PRE+SOF field (it's too long!)
I appreciate any clue.
Thank