dds blocks phase accumulator and lut

[preethi19]

Hi all i need to implement a BASK modulator in vhdl. And i learnt that the basic building block for this is DDS. Can anyone pls explain me about phase accumulator and ROM. Like i understand phase accumulator is just a counter. So say i just build a counter that increases with each clock cycle. And then the output of the accumulator can be given as the input(address) to ROM. And based on the address called the data is outputted from ROM. And then we use a phase to waveform converter to get the sine wave. But can anyone pls explain how to implement the above as blocks in vhdl.. Like say for example you need to build a simple counter and so on.. So i guess sine wave generator is the whole block within which is should instantiate the accumulator, ROM and waveform converter right??? Also please see this link https://books.google.ca/books?id=7-...h3Qwg3D#v=onepage&q=dds lut explained&f=false and pls scroll down wer u get a table. So i understand that table. Now i need to convert the ROM output to amplitude. How can i mention that for this value of ROM output the amplitude should keep toggling in a way to get a sine wave.. pls help me out.. Thank you!!!!

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Also kindly have a look at the lut in this link....
**broken link removed**
Now in this link they have entered values like 255,254,252, 249, 245, 239..... and so on.... now in the previous link in the table ROM outputs digital values. So why use 255, 254.. instead of binary... i am asking this becoz i have no idea of how to write the table. So now when these values be it 255 or binary value outputs from the ROM how to associate these values with a particular amplitude value... Do we need anpther register saying that for this ROM output this is the corresponding amplitude?? How is that done pls help me out.. I'm trying to do from scratch so little confused.. If anyone has some simple examples or sites pls let me know.. would be really helpful...

 

[KlausST]

Hi,

The Phase accumulator increments it's phase value with every clock cycle.
It has an input to adjust step size. The step size is proportional to the output frequency of the DDS.
If you set the step size to zero you will see zero output frequency.
Usually the bit width is selected to achieve the resulting frequency resolution.
How to interprete the value is up to the programmer. Often one interpretes the counter value to be 0..360 degree of the output signal.

Imagine a 16 bit counter. It counts from 0...65535. But you may interprete this as 0 ...360°.Then the angular resolution is 360°/65536.

*******
ROM values, amplitude values...
The digital output of the DDS usually is fed to a DAC. In your example it seems to be a 8 bit DAC, because of the value "255".

You wonder why there are values like "255" instead of binary.
You may write "255", "0xFF" or "0b11111111" but the result is always the same. These are just different representations of the same value.
It's on the programmer's taste how to write it.

Try to write the values in a way that other people know what numbering system you use. "00010" is ambiguous.

Klaus

 

[preethi19]

Thank you for the reply. I'm sorry if i am asking very basic stuff but what exactly is step size. Pls see the simulation in this link **broken link removed** and then pls see this link **broken link removed**
In second link we can actually see a sine wave while in first link just a straight line(binary values) . So i am assuming the step size is rising the signal more than just from 0 to 1... its like from 0 to different values of amplitude wer we actually get a curve sine wave like in this link https://www.physi.uni-heidelberg.de/~angelov/VHDL/VHDL_SS09_Teil06.pdf (pls scroll down).. PLs correct me if i' wrong... I need to write the code now. ANd i am just going to build a 8-bit counter incrementing by binary value 0000 0001 for each clock cycle. For phase accumulator i need step size.. So what does this represent additionally to a 8-bit counter... This is the logic i am going to build. Need it for my project. So any corrections would be really great!!! thank you!!!

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Secondly after i build this phase accumulator (8- bit counter), should my next block that i write the code for be a ROM table block. So is it like i build a ROM table with address and data. Kindly check the table in this link
https://books.google.ca/books?id=7-...h3Qwg3D#v=onepage&q=dds lut explained&f=false

So now i just take say 3 bits (like in the link above) of the the 8 bit accumulator and input it to the ROM block. And i build the ROM table in a way that for the input i get, is checked with the ROM address and if it matches then output the corresponding value... Is this way correct??? If it is can someone pls tell how i can make one block's output to be checked with the input/address of another block. I have done this wer output of one block is given to another but it was in a way wer the output was an input to another block and a logical calculation was performed. but here i just need to make accumulator output check the address already stored in ROM table... can anyone give me a logic or eg how to do that... I hope so far till here i am clear with both accumulator and ROM table blocks.... Kindly help me out.. Thank you

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Also if i were to write a ROM table the above link had only 32 values. But for 8-bit counter i guess i should have 256 different address right referring to each output. So now as you said 0 to 256 is like 0 to 360 degree. So how am i supposed to split the 256 values that they correspond to each degree..... like say from 0 to so on value is 45 degree... then from this to this is 90 degree and from this value to this is 180 degree... how am i supposed to write the table correctly according to the phase... I found this code for ROM table.. https://www.edaboard.com/threads/117304/

Or should i just take 0,45,90,180,270 and 360... 6 different angles constituting the whole sine wave and then split 256 values for each angle giving like 42 values has 0 degree then next 42 has 45 degree and then so on till 360 degree. so 42 values of 256 values x6( the 6 degree)=256. I am very confused in this part. pls help...

 

[Dan Mills]

The stepsize is the frequency tuning word, if your phase accumulator is B bits wide, and the stepsize ix X then the frequency at the output of X * Fs/(2^B), B is typically something in the 32 bit region to give a usefully fine tuning range.

Usually you only feed the upper bits of the phase accumulator to the ROM, in order to keep the ROM size reasonable, this causes some increase in spur levels but keeps the area requirement down.

Take advantage of whatever facilities your part has for block memories (Almost all fpgas have some way to do this), and write a little program in your favorite language to generate the initialization vector.

If you have a 8 bit ROM and are doing this the stupid way (There are symmetries you can exploit in a sine wave), then each value is simply K * sine (2*pi*location / (2^8)), which you will want to multiply to give an integer scaled to your DA converter or whatever (location is the rom address, 0 -> 255, K is the scale factor).

Regards, Dan.

 

[paulfjujo]

hello


maybe this XLS document can help you..
concerne DDS generator with AD9850 + PIC MCU

some DDS circuit have also special registers to adjust the phase value of the Output frequency.
i didn't use it myself..

View attachment AD9850_18F46K22.zip

 

[FvM]

but what exactly is step size

To answer the basic questions you are asking, you don't need to refer to five different books and papers. Instead it would be helpful to read one of it thoroughly.

A problem might be that each author is using partly different terms for the same thing, and is discussing a different hardware topology according to his specific problem scope.

To get things apart, you should focus on a simple DDS design and figure out the basic operation.

Some DDS designs in the quoted papers are simplified. If you don't need to tune frequency, it can be sufficient to use a simple up-counter in place of the phase accumulator, as in your first link, generating simply fclk/64 output frequency.

But in the general case, the frequency is given as fclk*tuningword/(2^phaseaccumulatorbitwidth). By making the phaseaccumulator and respecively the tuning word wide, e.g. 32 and more bits, you can achieve a fine frequency resolution.

The LUT ROM address width can be considerably smaller than the phase accumalator, it's only connected to the upper phase accumulator bits. See e.g. https://en.wikipedia.org/wiki/Numerically_controlled_oscillator

 

[rameshrai]

For BASK, perhaps DDS might not be needed(not sure). Sine table is stored in ROM, the output of this is fed to a mux that is used for selecting the amplitude value for ASK. The output of mux then goes to DAC. The output of DAC would be either sine or nothing hence BASK signal.

I think DDS should be used for phase and frequency modulated signal. But DDS should be used in case you want sophisticated signal generator even for BASK.