praveenlb
Full Member level 3
Board Layout Design Guidelines
To help ensure good signaling, consider the following board design guidelines:
• Avoid crossing splits in the power plane
• Separate supplies and/or flip-chip packaging to help avoid having SSO on the
controller, which collapses strobes/clocks
• Add low pass Vref filtering on the controller to improve noise margin
• Minimize Vref noise:
– Separate supplies or use flip-chip packaging
– Use similar spacing techniques that were used for signals to implement Vref
– Use the widest trace that is practical between decoupling capacitors and DIMM Vtt
pins
– Maintain a single reference (either ground or Vdd) between the decoupling capacitor
and the DRAM Vref pin.
• Minimize ISI by keeping impedances matched
• Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding returnpath
discontinuities
To help ensure good signaling, consider the following board design guidelines:
• Avoid crossing splits in the power plane
• Separate supplies and/or flip-chip packaging to help avoid having SSO on the
controller, which collapses strobes/clocks
• Add low pass Vref filtering on the controller to improve noise margin
• Minimize Vref noise:
– Separate supplies or use flip-chip packaging
– Use similar spacing techniques that were used for signals to implement Vref
– Use the widest trace that is practical between decoupling capacitors and DIMM Vtt
pins
– Maintain a single reference (either ground or Vdd) between the decoupling capacitor
and the DRAM Vref pin.
• Minimize ISI by keeping impedances matched
• Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding returnpath
discontinuities