ddr3 length matching

[patilpradeep]

My design consists of 5 DDR3 (64 bit + 8 bit ecc) . placed ddr in board is TOP & bottom format and i want to use flyby topology for routing. how to match the length in address group.???? what is the length tolerance???

 

[sivamani]

use tight tolerance around +/- 10 mils

 

[patilpradeep]

use tight tolerance around +/- 10 mils

1st memory is on topside & 2nd on bottom... for address minimum length is 60 mil & longest is 300 mils between 1st ddr to 2nd ddr ....because of top & bottom placement i cant maintain +/- 10mils .... is there anyother suggestions ? is that necessary match the length??


snapshot is for your reference.. by this you can understand my query..

 

[sivamani]

make sure that the stub length should be very minimum and match lengths chip wise . like maintain equal length from Controller to 1 st ddr3 as a group and 2nd set controller to 2nd DDR3 etc..

Do u have signal integrity tool?If yes then we can simulate how the stub is effecting signal from quality point of view..

And also please go thru write leveling and read leveling concept for better understanding on length matching...

refer
https://www.edaboard.com/threads/255905/

for some more details...

go thru the attached document it will really help you..

 

[patilpradeep]

Hello sivmani,

I ve on more doubt regarding X'talk report generated in batch simulation in allegro SI tool,



in this some nets showing odd & even Xtalk, what is tolerance(limits) for this Xtalk values????