hithesh123
Full Member level 6

I am lookign for some materials on DDR2 signalling (SSTL_18).
I read the Jedec specs. They just give the signalling levels.
I need a more basic intro sstl 18 signalling. Why Vref is used and the Vac and Vdc specs etc.
I read the Jedec specs. They just give the signalling levels.
I need a more basic intro sstl 18 signalling. Why Vref is used and the Vac and Vdc specs etc.