hastidot
Junior Member level 3
Hi all
I'm using MIG 3.4 for DDR2 controlling on virtex5.
I'm trying to write my own codes to write and read from memory.
As I am new to MIG ( and working with DDR2), I tried to follow the patter which is used as the MIG's synthesizable testbench uses. I read the UG086 many many times but i'm still confused about the data pattern ( and subsequently the address generation pattern).
As it is indicated in UG086:
The MIG test bench performs eight write commands and
eight read commands in an alternating fashion. The number of words in a write command
depends on the burst length. For a burst length of 4, the test bench writes a total of 32 data
words for all eight write commands (16 rise data words and 16 fall data words).
While generating my design, I chose the data width as 8, my DQ-width parameter is equal to 64 ( I'm confused about the relationship of these two parameters. which shows my design data width?), and the busrtlength=4.
First question:
I don't understand what is that: 8 consecutive read and write commands. As I can see in simulation results, the app_af_cmd is 0,1 periodically. What does it mean with 8?
Second:
I'm totally confused about the data patter. 32 data words (16fall and 16 rise) is interpreted as : FFFFFFFFFFFFFFFF0000000000000000
But what I see in siumlation is repetition of 16 data words like this in a write or read command. (means 16*128 bits of data in app_wdf_data !!!!!!!!!!!!!!!!!!!!!!!! )
Question 3:
As the BL=4, The address should be changed 4 times in a single write or read command. But it is changed 8 times in the simulation results.
Following is my simulation result (the ddr2_tb_top simulation result)
Please help me understand the manner:
The small rectangular in app_wdf_data are all 128 bits (I wanted to show you the number of data in each command so I had to zoom out the result)
it is something different from what is mentioned in the document.
I'm using MIG 3.4 for DDR2 controlling on virtex5.
I'm trying to write my own codes to write and read from memory.
As I am new to MIG ( and working with DDR2), I tried to follow the patter which is used as the MIG's synthesizable testbench uses. I read the UG086 many many times but i'm still confused about the data pattern ( and subsequently the address generation pattern).
As it is indicated in UG086:
The MIG test bench performs eight write commands and
eight read commands in an alternating fashion. The number of words in a write command
depends on the burst length. For a burst length of 4, the test bench writes a total of 32 data
words for all eight write commands (16 rise data words and 16 fall data words).
While generating my design, I chose the data width as 8, my DQ-width parameter is equal to 64 ( I'm confused about the relationship of these two parameters. which shows my design data width?), and the busrtlength=4.
First question:
I don't understand what is that: 8 consecutive read and write commands. As I can see in simulation results, the app_af_cmd is 0,1 periodically. What does it mean with 8?
Second:
I'm totally confused about the data patter. 32 data words (16fall and 16 rise) is interpreted as : FFFFFFFFFFFFFFFF0000000000000000
But what I see in siumlation is repetition of 16 data words like this in a write or read command. (means 16*128 bits of data in app_wdf_data !!!!!!!!!!!!!!!!!!!!!!!! )
Question 3:
As the BL=4, The address should be changed 4 times in a single write or read command. But it is changed 8 times in the simulation results.
Following is my simulation result (the ddr2_tb_top simulation result)
Please help me understand the manner:
The small rectangular in app_wdf_data are all 128 bits (I wanted to show you the number of data in each command so I had to zoom out the result)
it is something different from what is mentioned in the document.
