promach
Advanced Member level 4
1) For Preamble detection and postamble closure for a memory interface controller , could anyone explain how the following Figure 4 , Figure 5 and Figure 6 work to sample (or capture) the incoming DQ signal during DDR read activities ?
2) <-- Do anyone have idea on which exact independent technical note it is referring to ? I suppose for READ preamble, DQS is aligned with DQ , so why need to delay the incoming DQS strobe ? If it is due to DQS setup timing requirement for sampling DQ signal, then how would I implement the slight delay in verilog coding implementation ?
2) <-- Do anyone have idea on which exact independent technical note it is referring to ? I suppose for READ preamble, DQS is aligned with DQ , so why need to delay the incoming DQS strobe ? If it is due to DQS setup timing requirement for sampling DQ signal, then how would I implement the slight delay in verilog coding implementation ?