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DDR and DDR2 Memory clock frequency

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hithesh123

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I am a bit confused about the clock frequency of DDR vs DDR2.
For example, for DDR-400, the data rate is 400Mbps and for DDR2-400 the data rate is 400Mbps
For DDR-400, the memory clock is 200MHz.
For DDR2-400, the memory clock is 200MHz?????????????
By Memory clock, I mean the clock frequency that comes from the external memory controller like an FPGA or MCU.

Can I use DDR2-800 in place of DDR2-533?
 

Wikipedia is confusing.
Let's consider the SAM9G25 MCU. The app note uses DDR2-667 in the example schematic. But the max DDR clock frequency it can supply is just 133MHz
How is this possible?
Link - http://www.atmel.com/Images/doc6492.pdf
The DDR2 part used in the appnote is MT47H64M8B6-3, which is DDR2-667 (333MHz clock).
 

Oh if only you had read this bit.

That way you get where all the confusing numbers come from. Check the above link and see the bit about "DDR2-667C". The DDR2-667 you mention uses a clock frequency of 166 MHz, as you can see in the table there. The "667" in there is the data rate.
 
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Oh if only you had read this bit.

That way you get where all the confusing numbers come from. Check the above link and see the bit about "DDR2-667C". The DDR2-667 you mention uses a clock frequency of 166 MHz, as you can see in the table there. The "667" in there is the data rate.

Hi
I had the same confusion yesterday all day long and i figured it out:
first look at this picture:
**broken link removed**
then let's clear these words:
Memory clock: the clock which is inside the Memory part
I/O bus clock: the clock which is external to the memory part and is used between Memory controller and memory part.


As you see in the picture, it uses both DDR-400 (memory clock:200MHz, I/O bus clock 200MHz real) and DDR2-400(Memory clock=100MHz, I/O bus clock=200MHz real).
 

The term "memory clock" seems at least misleading to me. The memory chip's clock input frequency is always half the data rate, as the name DDR suggests, for all DDR, DDR2 and DDR3 devices. From a user's viewpoint, the difference is only in internal operation and shows up in latency and burst parameters.
 

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