DCM output division by clkdiv

[leily]

Hello,

I am using DCM of Virtex4. I want to divide the frequency through clkdiv by 20 (with an input of 120MHz I want an output clock of 6MHz) but the largest value permitted by DCM is 16. What should I do?
thank you,
Leily

 

[matbob]

Hi leily,

I think you could cascade the DCMs even though it is not a preferred solution. Google for help regarding cascading DCMs.

 

[muni123]

Opt for Base Synthesis mode in CTS where the min freq limit of your 6MHz applies only to input frequency.
Ref:https://www.fpgarelated.com/usenet/fpga/show/8044-1.php