dcm and clock issue of fpga

[ornko]

hi everyone!

i am new in fpga world . i need for a project a 40mhz clock, but due to bad isolation of cables the signal is really bad even at 10mhz. the clk signal has quite some ringing.

i am using a spartan 3 board xc3s1000, from what i understood from manual is that there is no internal clock to be used, but when trying to activate DCM i could see name of a pin clk_in. what is more there is a 50mhz clock mentioned, which i don't understand where is this clock generated.

my questions are:

• what is this 50mhz referring to?
• can i use it to supply the fpga (apply it to a GCLK pin)?
• how can i use successfully the DCM to apply an input of 4mhz (external) and obtain 40mhz (multiply) output clock which will be used for the fpga code to work and also supplied to the next board. I have created some code while doing the core configuration using dcm but what is the next step? on which part of my code should i add this generated clock?

 

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i am new in fpga world . i need for a project a 40mhz clock, but due to bad isolation of cables the signal is really bad even at 10mhz. the clk signal has quite some ringing.

Great you get stuck fixing a bad design using an FPGA, bad design decisions all around. This is what gave FPGAs a bad reputation at a couple of place I worked early in my career, they used them as glue logic to fix design flaws that should have been fixed at the source.

how can i use successfully the DCM to apply an input of 4mhz (external) and obtain 40mhz (multiply) output clock which will be used for the fpga code to work and also supplied to the next board.

To use a 4 MHz CLKIN you will have to use the DFS feature, which will allow you do go down to a 200 KHz CLKIN, but this means you can only use the CLKFX and CLKFX180 outputs of the DCM. The lower CLKIN limit when using the DCM outputs is 5 MHz.
see Table 38 in https://www.xilinx.com/support/documentation/data_sheets/ds529.pdf

what is this 50mhz referring to?
can i use it to supply the fpga (apply it to a GCLK pin)?

The 50 MHz you are referring to is probably the internal oscillator used for master mode configuration. Take a look at Table 46 in the same document above and you'll see that the default period can vary between 207-417ns for commercial and 195-417ns for industrial, you have to send a special configuration command to switch it to a higher clock frequency. But as you can see the clock is very inaccurate regardless of what setting it uses.

I did a quick look in the user guide, but didn't see any support for accessing the master configuration clock using the STARTUP primitive. I'm pretty sure this is something that got added much later like when they came out with Virtex 5. So no you can't use the master mode configuration clock, but it's not likely that you would want to as it's not accurate.

I have created some code while doing the core configuration using dcm but what is the next step? on which part of my code should i add this generated clock?

what do you mean by "which part of the code do you add this clock"? The core generator produces some files and you instantiate the DCM IP into your HDL code like any other IP. If you don't know about instantiating that then you're going to have to learn more basic HDL stuff before using the DCM.

 

[ornko]

First of all, thank you for your reply!

Second, I would like to fix the problems at the source, but I am just a student using the lab equipment.

Another problem that I faced was that I could not use lower input frequency, because I had to set fedback factor=none, otherwise the DLL was used and minimum input was 18MHz.

Last, I instantiate the new component, but during port map I get an error referring to the clock signal.

ERROR:Xst:2035 - Port <clk> has illegal connections. This port is connected to an input buffer and other components.

This is the generated IP core:

---

Code VHDL - [expand]
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COMPONENT mhz50_clk
    PORT(
        CLKIN_IN : IN std_logic;
        RST_IN : IN std_logic;          
        CLKFX180_OUT : OUT std_logic;
        CLKIN_IBUFG_OUT : OUT std_logic;
        LOCKED_OUT : OUT std_logic
        );
    END COMPONENT;
 
Inst_mhz50_clk: mhz50_clk PORT MAP(
        CLKIN_IN => ,
        RST_IN => ,
        CLKFX180_OUT => ,
        CLKIN_IBUFG_OUT => ,
        LOCKED_OUT => 
    );

---

This part is the instantiation with the assignment to my own pins:

---

Code VHDL - [expand]
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Inst_mhz50_clk: mhz50_clk PORT MAP(
        CLKIN_IN => clk,
        RST_IN => reset_n,
        CLKFX180_OUT => clk_a,
        CLKIN_IBUFG_OUT => open,
        LOCKED_OUT => locked
    );

---

How can I solve this error, while googling the error message, some people that had the same error solved it by making a copy of the CLK0 and use a different name to assign for CLKIN_IN, but I am not using CLK0 because I have to supply lower input clock, so I can not use DLL.

What can it be done in this case?

Thank you in advance!

 

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The instance in your code doesn't tell anyone how it is connected to the rest of the design. Out of context code might as well not be posted in the first place. So sorry I can't help you without knowing how it is connected to the rest of the FPGA.

In parts with a DCM the CLK_IN can only come from the PINs directly (through either a single or differential input buffer) or from a BUFG (cascaded DCM). If I recall correctly it can't go to both at the same time, to go to both you would have to us a PIN-IBUF(G/GDS)-BUFG-(processes|DCM), though I may be mistaken, it's been a long time since I worked with a part that didn't use the newer MMCM.