Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

DCDC design question, selecting frequency.

Status
Not open for further replies.

aslm

Full Member level 2
Joined
May 3, 2002
Messages
120
Helped
7
Reputation
14
Reaction score
2
Trophy points
1,298
Activity points
1,499
litzendrat wire

Hi all, asked a question about DCDC converters some time ago and I now starting to understand how to build one, but there is one question I have not been able to find an answer to.

Q: How is the switching frequency selected in an optimum way? (for cost and performance)

Some discussion on the subject...

With a higher frequency F the inductance L would be smaller, with a given toroide core this also gives less windings N and then the peak current I before L is saturated would be greater then given Bmax for the core material is dependent on NI for the inductor.

But what are the drawbacks, how high can the frequency be (how small can L be selected)? One parameter would be the switching losses in the transistor/mosfet used but are there more of the?

I have seen in books that F is selected at about 10-50kHz if they are written in the 1970’s and to about 50-300kHz if the book is written in the 1990’s, guess this is because there are better components (IC and T) today, but there is never any discussion about why to go up or down in F.

Im working on a 12V in, 20V and 10A out boost dcdc.

regards Me
 

goodboy_pl

Full Member level 5
Joined
Mar 12, 2002
Messages
253
Helped
16
Reputation
32
Reaction score
15
Trophy points
1,298
Activity points
3,119
it is true but normally for low volume production optimizing for every thing is not possible, thus simply a fixed frequency is considered and the SMPS is designed then power dissipation of each device is calculated to changing design variables for better performance. it needs some try and error. as a good starting point 100khz is very good because low cost cores at this freq. are available.

for a boost regulator, design variables are:
1.Rds(on) for conduction loss
2.switching time/switch size
3.inductance value which determines mode of operation (continous or discontinous mode), this is very important since higher inductnce will force the smps to continous mode which to some extent (10%-30%) is good for performance and output capacitor size reduction but higher than this level loop will be unstable.

for more info refer to www.powerint.com app. notes for transformer design of fly back (which is a coupled inductor in nature).
(NOTE: the manufacturer used a fixed freq. of 100khz in most of
products.)

BEST!
 

qaz

Newbie level 6
Joined
May 31, 2001
Messages
14
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
39
Ferrite core loss and copper loss.
 

RegUser_2

Full Member level 2
Joined
Dec 24, 2001
Messages
125
Helped
11
Reputation
22
Reaction score
9
Trophy points
1,298
Activity points
1,507
Ferite core loss is dominant, the copper loses are reduced for the low-frequency (100 kHz +) converters by using litzendrat wire). In the modern SMPS switch frequency above 1 MHz are used, where the cores are not needed.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top